公开(公告)号：DE68923863T2

公开(公告)日：1996-03-28

申请号：DE68923863

申请日：1989-12-11

Applicant: IBM

Inventor： CHANG ALBERT ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  O'QUIN III JOHN CLAUDE ,  O'QUIN II JOHN THOMAS

IPC: G06F12/08 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

公开(公告)号：BR9403514A

公开(公告)日：1995-06-20

申请号：BR9403514

申请日：1994-09-12

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNDS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/20

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE68921869D1

公开(公告)日：1995-04-27

申请号：DE68921869

申请日：1989-12-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F12/08 ,  G06F12/084 ,  G06F13/38

公开(公告)号：DE69419680T2

公开(公告)日：2000-03-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE69023677T2

公开(公告)日：1996-06-20

申请号：DE69023677

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

公开(公告)号：DE69021594T2

公开(公告)日：1996-05-02

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100T2

公开(公告)日：1995-10-05

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：DE69021594D1

公开(公告)日：1995-09-21

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100D1

公开(公告)日：1995-05-04

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：AU4276672A

公开(公告)日：1973-11-29

申请号：AU4276672

申请日：1972-05-25

Applicant: IBM

Inventor： MARING BLAYNE ELDON ,  NICHOLSON JAMES OTTO ,  RUST LYNN MICHAEL

IPC: G06F9/26 ,  G06F13/26 ,  G06F15/16