公开(公告)号：DE69322064T2

公开(公告)日：1999-07-01

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：DE69321929D1

公开(公告)日：1998-12-10

申请号：DE69321929

申请日：1993-12-27

Applicant: IBM

Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

公开(公告)号：AT173345T

公开(公告)日：1998-11-15

申请号：AT93120943

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107304A1

公开(公告)日：1994-07-09

申请号：CA2107304

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107046A1

公开(公告)日：1994-07-09

申请号：CA2107046

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.