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    2.
    发明专利
    未知

    公开(公告)号：DE69322064D1

    公开(公告)日：1998-12-17

    申请号：DE69322064

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

    6.
    发明专利
    未知

    公开(公告)号：DE69322064T2

    公开(公告)日：1999-07-01

    申请号：DE69322064

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

    7.
    发明专利
    未知

    公开(公告)号：AT173345T

    公开(公告)日：1998-11-15

    申请号：AT93120943

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

    Method and System for Single Cycle Dispatch of Multiple Instructions in a Superscalar Processor System
    8.
    发明专利
    Method and System for Single Cycle Dispatch of Multiple Instructions in a Superscalar Processor System 未知

    公开(公告)号：CA2107304A1

    公开(公告)日：1994-07-09

    申请号：CA2107304

    申请日：1993-09-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

    IPC: G06F9/38 ,  G06F15/16

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

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