公开(公告)号：US3602899A

公开(公告)日：1971-08-31

申请号：US3602899D

申请日：1969-06-20

Applicant: IBM

Inventor： LINDQUIST ARWIN B ,  PRICER WILBUR D ,  SEEBER ROBERT R

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: An associative memory matrix having a writable portion made up of bistable memory cells and a read-only portion made up of monostable memory cells. The memory may be used as a conventional memory by placing an address in the address field of an entry register, masking out all other bits and performing a match interrogation with the unmasked bits. Since the contents of the address portion (read-only memory) of each stored word are unique, the interrogation results in a single match at the location containing the address sought. Included is a circuit for determining whether no match, one match, or a multiple match has occurred.

公开(公告)号：US3601807A

公开(公告)日：1971-08-24

申请号：US3601807D

申请日：1969-01-13

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  PRICER WILBUR D

IPC: G06F13/40 ,  H04Q5/14 ,  H04M3/22

CPC classification number: G06F13/4022

Abstract: An input/output interface switching apparatus for switching I/O interfaces connecting I/O control units between channels. A matrix of transistor cross-point switches is provided for attaching one or more strings of control units to one or more channels. These strings of control unit are switched between the channels under configuration control. The cross-points are arranged so that a single failure within one interface affects at most only the channel to which the interface is associated. The switching matrix is physically centralized to minimize the number of I/O interface cables and connectors. The switching functions are, however, logically decentralized from a reliability standpoint so that a single component failure does not result in total switching system failure.

公开(公告)号：US3518631A

公开(公告)日：1970-06-30

申请号：US3518631D

申请日：1967-01-13

Applicant: IBM

Inventor： LINDQUIST ARWIN B ,  PRICER WILBUR D ,  SEEBER ROBERT R

IPC: G11C15/04 ,  G11C7/00 ,  G11C15/00

CPC classification number: G11C15/04

公开(公告)号：US3304505A

公开(公告)日：1967-02-14

申请号：US32897163

申请日：1963-12-09

Applicant: IBM

Inventor： PRICER WILBUR D

IPC: G01R23/00 ,  H03G5/16 ,  H03G5/22

CPC classification number: H03G5/22 ,  G01R23/00 ,  H03G5/16

公开(公告)号：CA1101992A

公开(公告)日：1981-05-26

申请号：CA183363

申请日：1973-10-15

Applicant: IBM

Inventor： PRICER WILBUR D

IPC: G11C11/401 ,  G11C11/404 ,  G11C11/24 ,  G11C11/40

Abstract: BIPOLAR TRANSISTOR MEMORY WITH CAPACITIVE STORAGE The memory is formed of an array of cells, each of which is coupled to the word and bit lines. Each cell comprises only a bipolar transistor coupled to a capacitor. The base terminal of the transistor is connected directly to the word line and either the emitter terminal or the collector terminal of the transistor may be coupled in series with capacitor. In one embodiment the transistor, in series with the capacitor, is connected between a bit/sense line and a reference voltage and in another embodiment it is connected between the bit line and a sense line. Information is stored in the capacitor by discharging the capacitor through the transistor and information is read out by charging the capacitor. During a read/erase operation the word line, which is normally at a quiescent voltage, is raised to a higher voltage to render the transistor conductive between its collector and emitter. Simultaneously, the bit line has impressed upon it a positive voltage. During a write operation the word line has impressed upon it a voltage which is between its quiescent voltage and its read/erase voltage. If a "0" is to be stored, the bit line is maintained at a high level and the capacitor charged. If a "1" is to be stored, the voltage on the bit line is substantially reduced so that the capacitor is discharged. During the read operations a signal is transmitted to the bit line if a "1" has been stored previously. BU9-72-002 -1-

公开(公告)号：DD130698A5

公开(公告)日：1978-04-19

申请号：DD19812177

申请日：1977-03-29

Applicant: IBM

Inventor： PRICER WILBUR D

IPC: G11C11/56 ,  G11C5/02 ,  G11C11/24 ,  G11C11/34 ,  G11C11/35 ,  H01L27/10 ,  H01L27/108

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.

公开(公告)号：CA731768A

公开(公告)日：1966-04-05

申请号：CA731768D

Applicant: IBM

Inventor： PRICER WILBUR D

公开(公告)号：DE69020852D1

公开(公告)日：1995-08-17

申请号：DE69020852

申请日：1990-08-17

Applicant: IBM

Inventor： PRICER WILBUR D ,  FAURE THOMAS B ,  MEYERSON BERNARD S ,  TURNBULL JOHN R ,  NESTORK WILLIAM

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C11/36 ,  H01L27/102

公开(公告)号：CA1226908A

公开(公告)日：1987-09-15

申请号：CA485185

申请日：1985-06-25

Applicant: IBM

Inventor： PRICER WILBUR D

IPC: G11C11/409 ,  G09G5/00 ,  G11C7/06 ,  H03F3/16 ,  H03F1/02

Abstract: Highly Sensitive High Performance Sense Amplifiers An improved voltage sensing circuit is provided which includes a pair of cross-coupled bipolar transistors coupled to a pair of signal nodes, a pair of cross-coupled field effect transistors coupled to the same pair of signal nodes and means for activating the bipolar transistors during a first period of time and then activating the field effect transistors. The bipolar transistors are preferably NUN transistors and the field effect transistors are preferably P channel transistors. The circuit may be conveniently fabricated in complementary metal oxide semiconductor (CMOS) technology.

公开(公告)号：CA1114504A

公开(公告)日：1981-12-15

申请号：CA300415

申请日：1978-04-04

Applicant: IBM

Inventor： JOSHI MADHUKAR L ,  PRICER WILBUR D

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/24

Abstract: CAPACITOR MEMORY WITH AN AMPLIFIED CELL SIGNAL A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.