CLEAN METHOD FOR RECESSED CONDUCTIVE BARRIERS
    11.
    发明申请
    CLEAN METHOD FOR RECESSED CONDUCTIVE BARRIERS 审中-公开
    用于阻塞导电障碍物的清洁方法

    公开(公告)号:WO0199181A2

    公开(公告)日:2001-12-27

    申请号:PCT/US0119241

    申请日:2001-06-14

    Abstract: A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer (26) employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant (wet etch) including hydrofluoric acid. The diffusion barrier layer (26) is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.

    Abstract translation: 根据本发明的用于清洁氧化的扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层(26),并提供包括氢氟酸的湿化学蚀刻剂(湿蚀刻)。 用湿化学蚀刻剂蚀刻扩散阻挡层(26),以从扩散阻挡层去除氧化物,使得通过使用湿式化学蚀刻剂,通过扩散阻挡层实现线性电性能。

    METHOD FOR POLISHING DIELECTRIC LAYERS USING FIXED ABRASIVE PADS
    12.
    发明申请
    METHOD FOR POLISHING DIELECTRIC LAYERS USING FIXED ABRASIVE PADS 审中-公开
    使用固定磨砂垫抛光电介质层的方法

    公开(公告)号:WO0249090A3

    公开(公告)日:2003-05-01

    申请号:PCT/US0144921

    申请日:2001-11-29

    CPC classification number: H01L21/31053

    Abstract: A method for polishing a dielectric layer containing silicon (16) provides a fluorine-based compound (34) during a polishing process. The dielectric layer is polished in the presence of the fluorine based compound to accelerate a polishing rate of the dielectric layer.

    Abstract translation: 用于抛光含硅(16)的电介质层的方法在抛光过程中提供氟基化合物(34)。 在氟基化合物的存在下对电介质层进行研磨,以加速电介质层的研磨速度。

    CERIA SLURRY AND PROCESS FOR THE CHEMICAL-MECHANICAL POLISHING OF SILICON DIOXIDE
    13.
    发明申请
    CERIA SLURRY AND PROCESS FOR THE CHEMICAL-MECHANICAL POLISHING OF SILICON DIOXIDE 审中-公开
    二氧化硅化学机械抛光的CERIA浆料和工艺

    公开(公告)号:WO0199170A3

    公开(公告)日:2002-05-02

    申请号:PCT/US0119656

    申请日:2001-06-20

    CPC classification number: H01L21/31053 C09G1/02

    Abstract: An aqueous based ceria slurry system and method for chemical mechanical polishing of semiconductor wafers, the slurry comprising less than 5 wt % abrasive cerium oxide particles and up to about the critical micelle concentration of a cationic surfactant, absent other abrasives, in a neutral to alkaline pH solution is disclosed. Also disclosed is slurry comprising a blend of surfactants including a pre-existing amount of anionic surfactant and an added amount of cationic and/or non-ionic surfactant.

    Abstract translation: 一种用于半导体晶片的化学机械抛光的水性二氧化铈浆料系统和方法,所述浆料包含小于5重量%的磨料氧化铈颗粒,并且高达约临界胶束浓度的阳离子表面活性剂,没有其它研磨剂,在中性至碱性 公开了pH溶液。 还公开了包含表面活性剂的共混物的浆料,其包括预先存在量的阴离子表面活性剂和加入量的阳离子和/或非离子表面活性剂。

    15.
    发明专利
    未知

    公开(公告)号:DE60003703T2

    公开(公告)日:2004-04-22

    申请号:DE60003703

    申请日:2000-09-05

    Abstract: An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.

    16.
    发明专利
    未知

    公开(公告)号:DE60003703D1

    公开(公告)日:2003-08-07

    申请号:DE60003703

    申请日:2000-09-05

    Abstract: An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.

    СПОСОБ ПОЛУЧЕНИЯ МНОГОСЛОЙНОЙ ЗАТВОРНОЙ СТРУКТУРЫ И ЕЕ УСТРОЙСТВО

    公开(公告)号:RU2498446C2

    公开(公告)日:2013-11-10

    申请号:RU2011132473

    申请日:2009-11-19

    Abstract: Изобретениеотноситсяк получениюмногослойнойзатворнойструктурыдляполевоготранзистора. Сущностьизобретения: способполучениямногослойнойзатворнойструктурыдляполевыхтранзистороввключаетформированиеметаллсодержащегослоянепосредственнонапервомслоенитридатитана TiN, покрывающемобластиполупроводниковойподложки, предназначенныедляпервогои второготиповполевыхтранзисторов, формированиезащитногослояпутемнанесениявторого TiN-слояповерхметаллсодержащегослоя, формированиерисунканавтором TiN-слоеи металлсодержащемслоедляпокрытиятолькопервойчастипервого TiN-слоя, покрывающейобласть, предназначеннуюдляполевыхтранзисторовпервоготипа, вытравливаниевторойчастипервого TiN-слоя, оставшейсяоткрытойприформированиирисунка, втовремякакперваячастьпервого TiN-слояостаетсязащищеннойоттравлениязасчетеезакрытияпоменьшеймеречастьютолщиныметаллсодержащегослоя, накоторомсформированрисунок, иформированиетретьего TiN-слоя, покрывающегообластьполупроводниковойподложки, предназначеннуюдлявтороготипаполевыхтранзисторов. Изобретениеобеспечиваетусовершенствованиетехнологииполучениямногослойнойзатворнойструктуры. 3 н. и 24 з.п. ф-лы, 9 ил.

    20.
    发明专利
    未知

    公开(公告)号:DE102005063468B4

    公开(公告)日:2009-05-20

    申请号:DE102005063468

    申请日:2005-11-15

    Applicant: QIMONDA AG IBM

    Abstract: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

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