公开(公告)号：GB2497201A

公开(公告)日：2013-06-05

申请号：GB201221413

申请日：2012-11-28

Applicant: IBM

Inventor： PEI CHENGWEN ,  WANG GENG ,  RAUSCH WERNER ,  NUMMY KAREN

IPC: H01L27/108

Abstract: A trench is formed in a semiconductor substrate 8, extending through a single crystal of semiconductor material 20, and is filled with a node dielectric layer 50 and at least a doped polycrystalline semiconductor fill portion 60A, 60B. A gate stack 32, 34, 38 for an access transistor is formed on the semiconductor substrate, and a gate spacer 36 is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion, the side wall of the trench may vertically coincide with the gate spacer and may contact the gate spacer. An epitaxial source region 53 and a polycrystalline semiconductor material portion 57 overlying fill material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. The epitaxial semiconductor material and the single crystal semiconductor material may have different lattice constants and may be n-doped, carbon doped silicon while the single crystal contains no carbon. The fill semiconductor material may be n-doped polysilicon or n-doped polycrystalline germanium. A shallow trench isolation (STI) structure may overlie the semiconductor fill material and may laterally contact one of its sidewalls. The STI structure may comprise a gate stack.

公开(公告)号：DE60137927D1

公开(公告)日：2009-04-23

申请号：DE60137927

申请日：2001-05-23

Applicant: IBM

Inventor： CULP JAMES ,  NAYAK JAWAHAR ,  RAUSCH WERNER ,  SHERONY MELANIE ,  VOLDMAN STEVEN ,  ZAMDMER NOAH

IPC: H01L21/00 ,  H01L27/04 ,  H01L21/822 ,  H01L29/10 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

公开(公告)号：AT425551T

公开(公告)日：2009-03-15

申请号：AT01931903

申请日：2001-05-23

Applicant: IBM

Inventor： CULP JAMES ,  NAYAK JAWAHAR ,  RAUSCH WERNER ,  SHERONY MELANIE ,  VOLDMAN STEVEN ,  ZAMDMER NOAH

IPC: H01L21/00 ,  H01L27/04 ,  H01L21/822 ,  H01L29/10 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

公开(公告)号：GB2346260B

公开(公告)日：2004-01-28

申请号：GB0001370

申请日：2000-01-24

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.