公开(公告)号：GB2497200A

公开(公告)日：2013-06-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer 20 on at least the sidewalls of a trench 10, and forming an undoped semiconductor fill material 25 in the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a second depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a first depth within the trench that is greater than a second depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill 35, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. In one embodiment a dielectric layer 15 is deposited before the metal contacting layer, the dielectric layer is also recessed. The trench may be formed in a semiconductor 4 on insulator 3 (SOI) structure placed on a base semiconductor 2 where the second depth is within the insulator layer and the first depth is within the base layer. The trench structure may be a capacitor in a memory device with the sidewalls and base of the trench forming the first electrode and the metal containing layer forming the second electrode, an access transistor may be included. In another embodiment the trench structure is a substrate through substrate via structure where the base is planarized to expose the undoped fill material, the metal layer and the dielectric layer, an electrical structure is then bonded to the metallic structure.

公开(公告)号：GB2494338B

公开(公告)日：2014-06-11

申请号：GB201221985

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.

公开(公告)号：GB2497200B

公开(公告)日：2014-02-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

公开(公告)号：GB2497201A

公开(公告)日：2013-06-05

申请号：GB201221413

申请日：2012-11-28

Applicant: IBM

Inventor： PEI CHENGWEN ,  WANG GENG ,  RAUSCH WERNER ,  NUMMY KAREN

IPC: H01L27/108

Abstract: A trench is formed in a semiconductor substrate 8, extending through a single crystal of semiconductor material 20, and is filled with a node dielectric layer 50 and at least a doped polycrystalline semiconductor fill portion 60A, 60B. A gate stack 32, 34, 38 for an access transistor is formed on the semiconductor substrate, and a gate spacer 36 is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion, the side wall of the trench may vertically coincide with the gate spacer and may contact the gate spacer. An epitaxial source region 53 and a polycrystalline semiconductor material portion 57 overlying fill material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. The epitaxial semiconductor material and the single crystal semiconductor material may have different lattice constants and may be n-doped, carbon doped silicon while the single crystal contains no carbon. The fill semiconductor material may be n-doped polysilicon or n-doped polycrystalline germanium. A shallow trench isolation (STI) structure may overlie the semiconductor fill material and may laterally contact one of its sidewalls. The STI structure may comprise a gate stack.

公开(公告)号：DE102012220824B4

公开(公告)日：2015-07-23

申请号：DE102012220824

申请日：2012-11-15

Applicant: IBM

Inventor： NUMMY KAREN A ,  PEI CHENGWEN ,  RAUSCH WERNER A ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

Abstract: Halbleiterstruktur, aufweisend: einen in einem Halbleitersubstrat angeordneten Graben, der sich in einer Halbleiterschicht erstreckt, welche ein erstens monokristallines Halbleitermaterial aufweist, und der mit einer Knotendielektrikumsschicht und mindestens einem leitfähigen Füllmaterialabschnitt gefüllt ist, wobei der mindestens eine leitfähige Füllmaterialabschnitt einen dotierten Halbleiterfüllungsabschnitt aufweist, der seitlich mit dem ersten monokristallinen Halbleitermaterial in Kontakt steht; und eine Source-Zone, die in die Halbleiterschicht eingebettet ist und ein anderes monokristallines Halbleitermaterial aufweist, welches sich von dem ersten monokristallinen Halbleitermaterial unterscheidet und epitaxial an dem monokristallinen Halbleitermaterial ausgerichtet ist und einen epitaxialen Halbleitermaterialabschnitt bildet; und einen polykristallinen Halbleitermaterialabschnitt, der mit einer obersten horizontalen Fläche des dotierten Halbleiterfüllungsabschnitts in Kontakt steht und ein gleiches Material wie die Source-Zone aufweist und mit der Source-Zone in Kontakt steht.

公开(公告)号：GB2506031A

公开(公告)日：2014-03-19

申请号：GB201320434

申请日：2012-05-31

Applicant: IBM

Inventor： PEI CHENGWEN ,  WANG GENG ,  ZHANG YANLI

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth d 1 around a gate structure on the semiconductor layer, forming a disposable spacer 58 around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth d2 greater than the first depth d1. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region 16 and an integrated epitaxial drain and drain extension region 18. A replacement gate structure can be formed after deposition and of a planarization dielectric layer 70 and subsequent removal of the gate structure and laterally expand the gate cavity 59 over expitaxial source 16 and drain extension regions 18. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

公开(公告)号：DE102012220824A1

公开(公告)日：2013-06-06

申请号：DE102012220824

申请日：2012-11-15

Applicant: IBM

Inventor： NUMMY KAREN A ,  PEI CHENGWEN ,  RAUSCH WERNER A ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

Abstract: Ein Graben wird in einem Halbleitersubstrat gebildet und mit einer Knotendielektrikumsschicht und mindestens einem leitfähigen Füllmaterialabschnitt gefüllt, welcher als innere Elektrode fungiert. Der mindestens eine leitfähige Füllmaterialabschnitt weist einen dotierten polykristallinen Halbleiterfüllungsabschnitt auf. Auf dem Halbleitersubstrat wird ein Gate-Stapel für einen Zugriffstransistor gebildet, und um den Gate-Stapel herum wird ein Gate-Abstandhalter gebildet. Zwischen einer äußeren Seitenwand des Gate-Abstandhalters und einer Seitenwand des dotierten polykristallinen Halbleiterfüllungsabschnitts wird ein Source/Drain-Graben gebildet. Eine epitaxiale Source-Zone und ein polykristalliner Halbleitermaterialabschnitt werden gleichzeitig durch ein selektives Epitaxieverfahren gebildet, so dass die epitaxiale Source-Zone und der polykristalline Halbleitermaterialabschnitt miteinander ohne eine Lücke dazwischen in Kontakt stehen. Der polykristalline Halbleitermaterialabschnitt stellt einen robusten Leitweg mit niedrigem Widerstand zwischen der Source-Zone und der inneren Elektrode bereit.

公开(公告)号：DE112011100948T5

公开(公告)日：2013-01-24

申请号：DE112011100948

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: Eine integrierte Schaltung mit FinFETs (60a, b) und einem Metall-Isolator-Metall(MIM)-Fin-Kondensator (65) und Fertigungsverfahren werden offenbart. Das Verfahren beinhaltet das Bilden eines ersten FinFET (60a), der ein erstes Dielektrikum (25) und einen ersten Leiter (30) umfasst; das Bilden eines zweiten FinFET (60b), der ein zweites Dielektrikum (40) und einen zweiten Leiter (45) umfasst; und das Bilden eines Fin-Kondensators (65), der den ersten Leiter (25), das zweite Dielektrikum (40) und den zweiten Leiter (45) umfasst.

公开(公告)号：GB2510525A

公开(公告)日：2014-08-06

申请号：GB201408644

申请日：2012-11-12

Applicant: IBM

Inventor： CHENG KANGGUO ,  ERVIN JOSEPH ,  PEI CHENGWEN ,  TODI RAVI M ,  WANG GENG

IPC: H01L29/78

Abstract: A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

公开(公告)号：GB2506031B

公开(公告)日：2014-07-09

申请号：GB201320434

申请日：2012-05-31

Applicant: IBM

Inventor： PEI CHENGWEN ,  WANG GENG ,  ZHANG YANLI

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.