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    Low-power organic light emitting diode pixel circuit
    13.
    发明专利
    Low-power organic light emitting diode pixel circuit 未知

    公开(公告)号：AU2002222301A1

    公开(公告)日：2002-07-16

    申请号：AU2002222301

    申请日：2001-12-21

    Applicant: IBM

    Inventor： SANFORD JAMES LAWRENCE ,  SCHLIG EUGENE STEWART

    IPC: H01L51/50 ,  G09F9/30 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  G11C11/419 ,  H01L27/32

    Abstract: A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complimentary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.

    ANALOG TO DIGITAL CONVERTER
    14.
    发明专利
    ANALOG TO DIGITAL CONVERTER 未知

    公开(公告)号：DE3279878D1

    公开(公告)日：1989-09-14

    申请号：DE3279878

    申请日：1982-05-24

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART

    IPC: H03M1/44 ,  H03M1/00 ,  H03M1/38

    Abstract: A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The converter includes one stage for each bit desired in the output bit stream so that a converter having n stages provides an n bit digital word corresponding to the input analog signal charge. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage.The Figure shows a three stage converter. In the initial stage, the reference charge packet (Q r ) from generator (CG) is halved by splitter (51) and the halved charged held by (FET FG1). The input charge is held on (FET FG2) and the two charges compared at (C1). The result of the comparison is delayed via delay stages (DR) and also used to control switches (SW1, SW2). In the intermediate or typical stage, the comparator (C 2 ) similarly compares charges held on (FET FG3 and FG4). the magnitude of the charges to be compared is determined by the setting of the switches (SW1, SW2). The final stage similar to a typical stage but includes charge drums D.The stages implements the algorithmwhere b n , is 0 or 1 depending on the comparison ( ) and b x is the inverse of bx.

    ANALOG-TO-DIGITAL CONVERTER INCLUDING A CHARGE SPLITTER
    15.
    发明专利
    ANALOG-TO-DIGITAL CONVERTER INCLUDING A CHARGE SPLITTER 未知

    公开(公告)号：DE3168853D1

    公开(公告)日：1985-03-28

    申请号：DE3168853

    申请日：1981-03-12

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART

    IPC: H03M1/44 ,  H03M1/00

    Abstract: A charge coupled device analog-to-digital converter includes a plurality of charge storage stages (S1-S6) that are arranged in a serial pipeline register and are connected to pass input source charges (QS) from stage to stage down the pipeline register. A reference charge generator (9) and a charge splitter (11) at each stage generate two fixed reference signals (Qc, Q M ). The first of the reference signals (Qc) is compared by a comparator (7,107) to a source charge that is temporarily stored at the stage. The comparator generates a binary 1 if the source charge is greaterthan or equal to the first reference charge and a binary 0 if the source charge is less than the first reference charge. If a binary 1 is generated, only the stored contents of the stage pass to the next successive stage. However, if a binary 0 is generated, the charge contents of the stage is passed to a next successive stage and the second reference charge (Q M ) is also passed by a transfer gate (17, 117) to the next successive stage, where the charges are combined. Buffer registers (31) are provided to temporarily store the output bits of the comparators of the stages to form a digital word for each source charge packet as the packet and associated added charge components leave the pipeline.

    16.
    发明专利
    未知

    公开(公告)号：IT8025969D0

    公开(公告)日：1980-11-14

    申请号：IT2596980

    申请日：1980-11-14

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART

    IPC: G11C8/16 ,  G11C11/411 ,  G11C

    Abstract: A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array.

    18.
    发明专利
    未知

    公开(公告)号：DE69115866D1

    公开(公告)日：1996-02-08

    申请号：DE69115866

    申请日：1991-10-10

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART ,  YAO YING LUH

    IPC: H04N1/04 ,  G06T1/00 ,  H04N1/48 ,  H04N9/04 ,  H04N1/46

    Abstract: An electronic imaging system develops red, green and blue images of a document in a single pass of the document through the system. The system includes an image sensor which has three time delay and integration (TDI) sensor arrays. Each sensor array is configured to have two optically masked rows of charge coupled devices (CCD's) for every row of CCD's that is used for imaging. The sensor arrays are arranged so that the first row of imaging CCD's on any two successive arrays are separated by a distance of an integer, K, times three times the height of a picture element (pel) of the image of the document that is projected onto the image sensor, plus or minus one pel height. The spectral component of the image of the document that is projected onto the image sensor is changed in sequence from red, to green, to blue. As the spectral component projected onto the image sensor is changed, the image of the document is scanned down the image sensor by a distance of one pel height. By this scheme, each line of pels in the document is imaged in each of the sensor arrays in a respectively different spectral component. A document may be imaged in all three colors in a single pass through the system without having dedicated filters for each of the separate sensor arrays.

    CHARGE COUPLED DEVICE STRUCTURES AND METHODS OF USING SUCH STRUCTURE TO COMPARE TWO CHARGE PACKAGES
    19.
    发明专利
    CHARGE COUPLED DEVICE STRUCTURES AND METHODS OF USING SUCH STRUCTURE TO COMPARE TWO CHARGE PACKAGES 未知

    公开(公告)号：DE3472861D1

    公开(公告)日：1988-08-25

    申请号：DE3472861

    申请日：1984-11-14

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART ,  CHAMBERLAIN SAVVAS GEORGIOU

    IPC: G11C27/04 ,  G01R29/24 ,  G06G7/14 ,  G06G7/25 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/768 ,  H01L29/772 ,  H01L27/10

    Abstract: Two unknown charge packets are stored in adjacent potential wells of equal depth in a charge coupled device. The charge packets are then merged by changing the potential on an intermediate merge electrode to remove a potential barrier between the two wells. The potential barrier is then re-established, and a current is induced through one of the electrodes which established the two wells of equal depth, and that current is integrated as a measure of the original absolute difference between the two packets. The potential wells 24, 26 are set-up by signals VR and VG and thereafter charges Q1 Q2 introduced while signal VM on merge electrode 16 maintains the wells isolated. The charges are then merged by varying the signal VM which is then restored to its former value to isolate the wells. Various transient currents occur resulting in transistor 28 or 30 conducting charge away from capacitor 38. The potential change at output 36 represents the charge difference.

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