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公开(公告)号：BR8900568A
公开(公告)日：1989-10-10
申请号：BR8900568
申请日：1989-02-09
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BORDEN TERRY LEE , BUTWELL JUSTIN RALPH , CLARK CARL EDWARD , GANEK ALAN GEORGE , LUM JAMES , MALL MICHAEL GERARD , PAGE DAVID RICHARD , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.
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公开(公告)号：DE69231611T2
公开(公告)日：2001-07-05
申请号：DE69231611
申请日：1992-10-30
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN , SINHA BHASKAR
Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.
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公开(公告)号：AT198381T
公开(公告)日：2001-01-15
申请号：AT92118610
申请日：1992-10-30
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , PLAMBECK KENNETH ERNEST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN , SINHA BHASKAR
Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.
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公开(公告)号：DE3854616T2
公开(公告)日：1996-06-13
申请号：DE3854616
申请日：1988-12-12
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BORDEN TERRY LEE , BUTWELL JUSTIN RALPH , CLARK CARL EDWARD , GANEK ALAN GEORGE , LUM JAMES , MALL MICHAEL GERARD , PAGE DAVID RICHARD , PLAMBECK KENNETH ERNST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.
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公开(公告)号：DE68923627T2
公开(公告)日：1996-04-25
申请号：DE68923627
申请日：1989-01-05
Applicant: IBM
Inventor： SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
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Patent Agency Ranking
公开(公告)号：DE68924833D1
公开(公告)日：1995-12-21
申请号：DE68924833
申请日：1989-08-23
Applicant: IBM
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公开(公告)号：DE3854616D1
公开(公告)日：1995-11-30
申请号：DE3854616
申请日：1988-12-12
Applicant: IBM
Inventor： BAUM RICHARD IRWIN , BORDEN TERRY LEE , BUTWELL JUSTIN RALPH , CLARK CARL EDWARD , GANEK ALAN GEORGE , LUM JAMES , MALL MICHAEL GERARD , PAGE DAVID RICHARD , PLAMBECK KENNETH ERNST , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.
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公开(公告)号：DE3279400D1
公开(公告)日：1989-03-02
申请号：DE3279400
申请日：1982-06-08
Applicant: IBM
Inventor： BROWN DAVID TRENT , RAIN DON WARREN , SCHMALZ RICHARD JOHN
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公开(公告)号：DE3176834D1
公开(公告)日：1988-09-08
申请号：DE3176834
申请日：1981-02-16
Applicant: IBM
Inventor： BUTWELL JUSTIN RALPH , SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: The specification discloses an address control means in a data processing system which associates access registers (AR's 46) with the general purpose registers (GPR's 17) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The arrangement allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data. The arrangement obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.
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公开(公告)号：DE3278586D1
公开(公告)日：1988-07-07
申请号：DE3278586
申请日：1982-02-02
Applicant: IBM
Inventor： SCALZI CASPER ANTHONY , SCHMALZ RICHARD JOHN
Abstract: The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses within the address spaces. An address space mask register (41) has a plurality of digit positions which receive the respective digit values comprising a particular GR mask. A respective digit position is selected by a base GR address signal provided by a storage address request from a CPU instruction decoder (6). The particular value of the selected digit in the mask register controls the selection among a plurality of STO registers, which designate a plurality of simultaneously available address spaces. The selected base GR is used in a System/370 B, D or X, B, D type of logical storage address representation. A base GR explicitly contains an intra-address-space base value. The GR mask assigns an implicit inter-address-space designation to the base GR in a simple manner which is handled by conventional address translation hardware. The available address spaces are respectively designated in STO registers by segment table addresses (called STOs). Any number of STO registers (and available address spaces) may be provided up to the radix of each digit in the GR mask. The executing program exists in the address space designated in one of the STO registers. A plurality of storage protect key registers (60) are respectively associated with the STO registers to control the accessing authorized to the executing program within each available address space. The key value may be independently authorized and provided for each available address space. A cross-memory implementation results which enables a compatible extension of the IBM System/ 370 architecture by permitting the unrestricted use of all S/ 370 instructions including storage-to-storage (SS) instructions that can access data simultaneously in plural address spaces in non-privileged state.
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