公开(公告)号：AU2003278329A1

公开(公告)日：2004-06-23

申请号：AU2003278329

申请日：2003-10-22

Applicant: IBM

Inventor： NORSTRAND ALBERT JAMES VAN JR ,  FEISTE KURT ALAN ,  SHIPPY DAVID

IPC: G06F7/38 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00

Abstract: A system and method is provided for improving throughput of an in-order multithreading processor. A dependent instruction is identified to follow at least one long latency instruction with register dependencies from a first thread. The dependent instruction is recycled by providing it to an earlier pipeline stage. The dependent instruction is delayed at dispatch. The completion of the long latency instruction is detected from the first thread. An alternate thread is allowed to issue one or more instructions while the long latency instruction is being executed.

公开(公告)号：DE60320026T2

公开(公告)日：2009-05-14

申请号：DE60320026

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：DE60320026D1

公开(公告)日：2008-05-08

申请号：DE60320026

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：AU2003302824A8

公开(公告)日：2004-06-30

申请号：AU2003302824

申请日：2003-11-21

Applicant: IBM

Inventor： JOHNS CHARLES RAY ,  TRUONG THUONG QUANG ,  HOFSTEE HARM PETER ,  SHIPPY DAVID ,  KAHLE JAMES ALLAN ,  DAY MICHAEL NORMAN

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：AU2003302824A1

公开(公告)日：2004-06-30

申请号：AU2003302824

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.