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    Decimal and binary floating point arithmetic calculations
    12.
    发明专利
    Decimal and binary floating point arithmetic calculations 未知

    公开(公告)号：GB2530990A

    公开(公告)日：2016-04-13

    申请号：GB201417582

    申请日：2014-10-06

    Applicant: IBM

    Inventor： MICHAEL KROENER ,  SILVIA MELITTA MUELLER ,  STEVEN R CARLOUGH ,  MICHAEL KLEIN ,  KERSTIN SCHELM ,  PETRA LEBER ,  JUERGEN HAESS

    IPC: G06F7/485 ,  G06F7/491

    Abstract: A decimal floating point unit for performing add or subtract calculations on a first (100) and second operand (101) comprising unpacking S200 the first and second operand such as by formatting 128 bit width mantissa to be 136 bit wide; conditionally swapping S202 the first and second operand, if an exponent (104) of the first operand is less than an exponent (105) of the second operand, and aligning S204, S206 the operands based on the exponent difference and a number of leading zeroes in the operand with the larger exponent. Adding or subtracting the operands S208 is performed on the aligned operands with normalizing and rounding of the result which is then packed S210. Binary floating point arithmetic can also be performed on the decimal floating point unit which may be pipelined.

    Digit Validation check control in instruction execution
    13.
    发明专利
    Digit Validation check control in instruction execution 未知

    公开(公告)号：GB2595191B

    公开(公告)日：2022-09-21

    申请号：GB202112124

    申请日：2020-01-27

    Applicant: IBM

    Inventor： CEDRIC LICHTENAU ,  REID COPELAND ,  PETRA LEBER ,  JONATHAN BRADBURY ,  SILVIA MELITTA MUELLER ,  XIN GUO

    IPC: G06F11/10 ,  G06F9/30

    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

    Instruction handling for accumulation of register results in a microprocessor
    14.
    发明专利
    Instruction handling for accumulation of register results in a microprocessor 未知

    公开(公告)号：GB2603653A

    公开(公告)日：2022-08-10

    申请号：GB202202229

    申请日：2020-07-21

    Applicant: IBM

    Inventor： BRIAN THOMPTO ,  MAARTEN BOERSMA ,  ANDREAS WAGNER ,  JOSE EDUARDO MOREIRA ,  HUNG LE ,  SILVIA MELITTA MUELLER ,  DUNG NGUYEN

    IPC: G06F9/30

    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

    INSTRUCCION DECIMAL DE MULTIPLICACION Y DESPLAZAMIENTO.
    16.
    发明专利
    INSTRUCCION DECIMAL DE MULTIPLICACION Y DESPLAZAMIENTO. 未知

    公开(公告)号：MX2019003610A

    公开(公告)日：2019-06-17

    申请号：MX2019003610

    申请日：2017-09-21

    Applicant: IBM

    Inventor： JONATHAN BRADBURY ,  REID COPELAND ,  SILVIA MELITTA MUELLER ,  STEVEN CARLOUGH

    IPC: G06F7/491 ,  G06F5/01 ,  G06F7/52

    Abstract: Se ejecuta una instrucción para llevar a cabo una operación de multiplicación y desplazamiento. La ejecución incluye multiplicar un primer valor y un segundo valor obtenido por la instrucción para obtener un producto. El producto se desplaza en una dirección especificada por una cantidad seleccionada definida por el usuario para proporcionar un resultado, y el resultado se coloca en una ubicación seleccionada. El resultado será utilizado en el procesamiento dentro del entorno de computación.

    Digit Validation check control in instruction execution
    19.
    发明专利
    Digit Validation check control in instruction execution 未知

    公开(公告)号：GB2595191A

    公开(公告)日：2021-11-17

    申请号：GB202112124

    申请日：2020-01-27

    Applicant: IBM

    Inventor： CEDRIC LICHTENAU ,  REID COPELAND ,  PETRA LEBER ,  JONATHAN BRADBURY ,  SILVIA MELITTA MUELLER ,  XIN GUO

    IPC: G06F9/455

    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

    Fused-multiply-add floating-point operations on 128 bit wide operands
    20.
    发明专利
    Fused-multiply-add floating-point operations on 128 bit wide operands 未知

    公开(公告)号：GB2573239A

    公开(公告)日：2019-10-30

    申请号：GB201911402

    申请日：2018-01-08

    Applicant: IBM

    Inventor： MICHAEL KLAUS KROENER ,  UDO KRAUTZ ,  TINA BABINSKY ,  SILVIA MELITTA MUELLER ,  ANDREAS WAGNER

    IPC: G06F7/483 ,  G06F7/544

    Abstract: A floating-point unit (10), being configured to implement a fused-multiply-add operation on three 128 bit wide operands (100, 102, 104), comprising: (i) a 113×113-bit multiplier (14); (ii) a left shifter (18); (iii) a right shifter (20); (iv) a select circuit (24) comprising a 3-to-2 compressor (25); (v) an adder (26) connected to the dataflow from the select circuit (24); (vi) a first feedback path (36) connecting a carry output (91) of the adder (26) to the select circuit (24); (vii) a second feedback path (38) connecting the output of the adder (26) to the shifters (18, 20) for passing an intermediate wide result (86) through the shifters (18, 20).

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