公开(公告)号：EP2396812A4

公开(公告)日：2012-08-01

申请号：EP10767544

申请日：2010-04-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  MO RENEE T ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66795

公开(公告)号：EP1875507A4

公开(公告)日：2009-08-05

申请号：EP06740000

申请日：2006-03-30

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：EP1875516A4

公开(公告)日：2008-08-13

申请号：EP06739771

申请日：2006-03-27

Applicant: IBM

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L21/8244 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。 体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。 阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：WO2012118568A3

公开(公告)日：2012-11-08

申请号：PCT/US2012020728

申请日：2012-01-10

Applicant: IBM ,  TEKLEAB DANIEL G ,  HUNG TRAN H ,  SLEIGHT JEFFREY W ,  CHIDAMBARRAO DURESETI

Inventor： TEKLEAB DANIEL G ,  HUNG TRAN H ,  SLEIGHT JEFFREY W ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner (61) and outer gate (50) separated from each other by a tubular shaped epitaxially grown silicon layer, and a source (35) and drain (31) respectively separated by spacers (51, 41) surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer (30); forming an outer gate surrounding the cylindrical Si layer (30) and positioned between a bottom spacer (41) and a top spacer (51); growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.

Abstract translation: 纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。 纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部（61）和外部栅极（50），以及分别由间隔物（51,41）分隔的源极（35）和漏极（31） ）围绕管状内门和外门。 形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层（30）; 形成围绕所述圆柱形Si层（30）并定位在底部间隔物（41）和顶部间隔物（51）之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

公开(公告)号：WO2006113061A2

公开(公告)日：2006-10-26

申请号：PCT/US2006011167

申请日：2006-03-27

Applicant: IBM ,  CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L29/94

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种包括具有SOI区域和体硅区域的衬底的6T-SRAM半导体结构，其中SOI区域和体硅区域具有相同或不同的晶体取向; 将SOI区域与本体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层的顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：WO2011084975A3

公开(公告)日：2011-12-29

申请号：PCT/US2011020173

申请日：2011-01-05

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

Abstract translation: 在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。 在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。

公开(公告)号：WO2007115146B1

公开(公告)日：2008-06-05

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

公开(公告)号：DE112013001158T5

公开(公告)日：2014-11-13

申请号：DE112013001158

申请日：2013-02-19

Applicant: IBM

Inventor： SLEIGHT JEFFREY W ,  CHANG JOSEPHINE B ,  LAUER ISAAC ,  NARASIMHA SHREESH

IPC: H01L29/78 ,  H01L21/336

Abstract: Es werden nichtplanare Halbleitereinheiten bereitgestellt, welche mindestens einen Halbleiter-Nanodraht 18'' umfassen, der über einer Halbleiteroxidschicht (26) aufgehängt ist, die auf einem ersten Abschnitt (100) eines massiven Halbleitersubstrats vorhanden ist. Ein Endsegment des mindestens einen Halbleiter-Nanodrahts ist an einer ersten Halbleiterkontaktzone (20A) befestigt und ein anderes Endsegment des mindestens einen Halbleiter-Nanodrahts ist an einer zweiten Halbleiterkontaktzone (20B) befestigt. Die erste und zweite Halbleiterkontaktzone sind über einem zweiten Abschnitt (102) des massiven Halbleitersubstrats angeordnet, welcher von dem ersten Abschnitt (100) vertikal versetzt ist, und stehen in direktem Kontakt mit diesem. Die Struktur umfasst ferner ein Gate (27), welches einen Mittelabschnitt (18C) des mindestens einen Halbleiter-Nanodrahts umgibt, eine Source-Zone (40, 50A), welche auf einer ersten Seite des Gates angeordnet ist, und eine Drain-Zone (40', 50B), welche auf einer zweiten Seite des Gates angeordnet ist, die der ersten Seite des Gates gegenüber liegt.

公开(公告)号：WO2013151625A2

公开(公告)日：2013-10-10

申请号：PCT/US2013026779

申请日：2013-02-20

Applicant: IBM

Inventor： CHANG LELAND ,  LIN CHANG-HSUN ,  LO SHIH-HSIEN ,  SLEIGHT JEFFREY W

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/6659

Abstract: A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.

Abstract translation: 一种静态随机存取存储器制造方法包括在衬底上形成栅极堆叠，在栅极叠层附近形成隔离间隔物，隔离间隔物和栅极叠层具有栅极长度，形成与栅极堆叠相邻的源极和漏极区域，其产生有效的 栅极长度，其中源极和漏极区域由改变栅极长度和有效栅极长度之间的差异的低延伸剂量注入形成。

公开(公告)号：WO2007115146A3

公开(公告)日：2008-04-24

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。