公开(公告)号：CA2434875A1

公开(公告)日：2002-07-25

申请号：CA2434875

申请日：2002-01-11

Applicant: IBM

Inventor： STAMPER ANTHONY ,  RICE MICHAEL ,  NAKOS JAMES ,  GROVES ROBERT ,  BALLANTINE ARNE ,  LUND JENNIFER

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery (420) within an integrated circuit for providing voltage to low-current electronic devices (900) that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices (900) on a semiconductor wafer (402), followed by Back-End-Of-Line (BEOL) integration f or wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery (420) is formed during BEOL integration within one or more wiring levels, and the conductive metallization (432,434,442,444) conductively couples positive (42 4) and negative (422) terminals of the battery to the electronic devices (900). The battery (420) may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：CA2787130C

公开(公告)日：2018-07-24

申请号：CA2787130

申请日：2011-06-15

Applicant: IBM

Inventor： STAMPER ANTHONY ,  JAHNES CHRISTOPHER VINCENT

IPC: B81B3/00

Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

公开(公告)号：DE112011102124B4

公开(公告)日：2015-11-26

申请号：DE112011102124

申请日：2011-06-15

Applicant: IBM

Inventor： JAHNES CHRISTOPHER VINCENT ,  STAMPER ANTHONY

IPC: B81B3/00

Abstract: Verfahren zum Ausbilden eines Arms eines mikroelektromechanischen Systems (MEMS), aufweisend: Ausbilden einer unteren Elektrode (38) auf einer Opferschicht (18); Ausbilden einer Isolatorschicht (40) auf der unteren Elektrode (38); und Ausbilden einer oberen Elektrode (44) über dem Isolatormaterial (40) auf der Oberseite der unteren Elektrode (38), wobei die obere Elektrode (44) zumindest teilweise mit der unteren Elektrode (38) in Kontakt steht, wobei die untere Elektrode (38) und die obere Elektrode (44) aus demselben Material ausgebildet werden. wobei das Ausbilden der unteren Elektrode und der oberen Elektrode ein Ausgleichen eines Metallvolumens der unteren Elektrode und der oberen Elektrode derart aufweist, dass die untere Elektrode (38) eine um einen Prozentsatz geringere Fläche als die obere Elektrode (44) aufweist und die Dicke der unteren Elektrode um einen Prozentsatz erhöht wird, um das Metallvolumen der Elektroden auszugleichen, sodass die Metallvolumina der unteren Elektrode (38) und der oberen Elektrode (44) übereinstimmen.

公开(公告)号：DE112011102124T9

公开(公告)日：2015-10-08

申请号：DE112011102124

申请日：2011-06-15

Applicant: IBM

Inventor： JAHNES CHRISTOPHER VINCENT ,  STAMPER ANTHONY

IPC: B81B3/00

Abstract: Verfahren zum Ausbilden eines Arms eines mikroelektromechanischen Systems (MEMS), aufweisend: Ausbilden einer unteren Elektrode (38) auf einer Opferschicht (18); Ausbilden einer Isolatorschicht (40) auf der unteren Elektrode (38); und Ausbilden einer oberen Elektrode (44) über dem Isolatormaterial (40) auf der Oberseite der unteren Elektrode (38), wobei die obere Elektrode (44) zumindest teilweise mit der unteren Elektrode (38) in Kontakt steht, wobei die untere Elektrode (38) und die obere Elektrode (44) aus demselben Material ausgebildet werden. wobei das Ausbilden der unteren Elektrode und der oberen Elektrode ein Ausgleichen eines Metallvolumens der unteren Elektrode und der oberen Elektrode derart aufweist, dass die untere Elektrode (38) eine um einen Prozentsatz geringere Fläche als die obere Elektrode (44) aufweist und die Dicke der unteren Elektrode um einen Prozentsatz erhöht wird, um das Metallvolumen der Elektroden auszugleichen, sodass die Metallvolumina der unteren Elektrode (38) und der oberen Elektrode (44) übereinstimmen.

公开(公告)号：AT539447T

公开(公告)日：2012-01-15

申请号：AT02784578

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT ,  FITZSIMMONS JOHN ,  KANE TERENCE ,  LUSTIG NAFTALI ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY ,  WANG YUN ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：CA2787161A1

公开(公告)日：2011-12-29

申请号：CA2787161

申请日：2011-06-15

Applicant: IBM

Inventor： STAMPER ANTHONY ,  JAHNES CHRISTOPHER VINCENT

IPC: B81C1/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System(MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.

公开(公告)号：CA2787130A1

公开(公告)日：2011-12-29

申请号：CA2787130

申请日：2011-06-15

Applicant: IBM

Inventor： STAMPER ANTHONY ,  JAHNES CHRISTOPHER VINCENT

IPC: B81B3/00

Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

公开(公告)号：GB2399451B

公开(公告)日：2005-08-17

申请号：GB0318083

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE ,  GROVES ROBERT ,  LUND JENNIFER ,  NAKOS JAMES ,  RICE MICHAEL ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：GB2391388A

公开(公告)日：2004-02-04

申请号：GB0322556

申请日：2002-03-25

Applicant: IBM

Inventor： ADAMS CHARLOTTE ,  STAMPER ANTHONY

IPC: H01L21/3105 ,  H01L21/311 ,  H01L23/522 ,  H01L21/768

Abstract: A method for fabricating a dual damascene coper interconnect which electrically contacts a damascene tungsten wiring level (190) comprising forming a first layer on a semiconductor substrate, a silicon nitride layer (140) on the first layer, and a silicon dioxide layer (150) on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by electrically insulating material. A continuous space (630) is formed by etching two contact throughs (910) through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact throughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.