公开(公告)号：DE60235872D1

公开(公告)日：2010-05-20

申请号：DE60235872

申请日：2002-02-07

Applicant: IBM

Inventor： ACOSTA RAUL ,  LUND JENNIFER ,  GROVES ROBERT ,  ROSNER JOANNA ,  CORDES STEVEN ,  CARASSO MELANIE

IPC: H01F17/00 ,  H01F41/04 ,  H01F17/02 ,  H01F27/36

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

公开(公告)号：AT463828T

公开(公告)日：2010-04-15

申请号：AT02711020

申请日：2002-02-07

Applicant: IBM

Inventor： ACOSTA RAUL ,  LUND JENNIFER ,  GROVES ROBERT ,  ROSNER JOANNA ,  CORDES STEVEN ,  CARASSO MELANIE

IPC: H01F17/00 ,  H01F41/04 ,  H01F17/02 ,  H01F27/36

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

公开(公告)号：CA2434875A1

公开(公告)日：2002-07-25

申请号：CA2434875

申请日：2002-01-11

Applicant: IBM

Inventor： STAMPER ANTHONY ,  RICE MICHAEL ,  NAKOS JAMES ,  GROVES ROBERT ,  BALLANTINE ARNE ,  LUND JENNIFER

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery (420) within an integrated circuit for providing voltage to low-current electronic devices (900) that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices (900) on a semiconductor wafer (402), followed by Back-End-Of-Line (BEOL) integration f or wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery (420) is formed during BEOL integration within one or more wiring levels, and the conductive metallization (432,434,442,444) conductively couples positive (42 4) and negative (422) terminals of the battery to the electronic devices (900). The battery (420) may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：AT478438T

公开(公告)日：2010-09-15

申请号：AT02725187

申请日：2002-03-13

Applicant: IBM

Inventor： ACOSTA RAUL ,  CARASSO MELANIE ,  CORDES STEVEN ,  GROVES ROBERT ,  LUND JENNIFER ,  ROSNER JOANNA

IPC: H01L29/82 ,  H01F17/00 ,  H01F17/04 ,  H01F17/06 ,  H01F27/00 ,  H01F27/06 ,  H01F41/04 ,  H01L21/02 ,  H01L27/08 ,  H01L29/00

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

公开(公告)号：GB2399451A

公开(公告)日：2004-09-15

申请号：GB0318083

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE ,  GROVES ROBERT ,  LUND JENNIFER ,  NAKOS JAMES ,  RICE MICHAEL ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery (420) within an integrated circuit for providing voltage to low-current electronic devices (900) that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices (900) on a semiconductor wafer (402), followed by Back-End-Of-Line (BEOL) integration for wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery (420) is formed during BEOL integration within one or more wiring levels, and the conductive metallization (432,434,442,444) conductively couples positive (424) and negative (422) terminals of the battery to the electronic devices (900). The battery (420) may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：AT388480T

公开(公告)日：2008-03-15

申请号：AT02768707

申请日：2002-08-26

Applicant: IBM

Inventor： JAHNES CHRISTOPHER ,  LUND JENNIFER ,  SAENGER KATHERINE ,  VOLANT RICHARD

IPC: B81B3/00 ,  H01H57/00 ,  B81C1/00 ,  G02B5/00 ,  G02B26/00 ,  G02B26/08 ,  H01H59/00

Abstract: A micro-electromechanical (MEM) RF switch provided with a deflectable membrane ( 60 ) activates a switch contact or plunger ( 40 ). The membrane incorporates interdigitated metal electrodes ( 70 ) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane ( 60 ), and is used to mechanically displace the switch contact ( 30 ). An RF gap area ( 25 ) located within the cavity ( 250 ) is totally segregated from the gaps ( 71 ) between the interdigitated metal electrodes ( 70 ). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity ( 250 ); at least one conductive path ( 20 ) integral to a first surface bordering the cavity; a flexible membrane ( 60 ) parallel to the first surface bordering the cavity ( 250 ), the flexible membrane ( 60 ) having a plurality of actuating electrodes ( 70 ); and a plunger ( 40 ) attached to the flexible membrane ( 60 ) in a direction away from the actuating electrodes ( 70 ), the plunger ( 40 ) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

公开(公告)号：GB2399451B

公开(公告)日：2005-08-17

申请号：GB0318083

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE ,  GROVES ROBERT ,  LUND JENNIFER ,  NAKOS JAMES ,  RICE MICHAEL ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.