公开(公告)号：DE60235872D1

公开(公告)日：2010-05-20

申请号：DE60235872

申请日：2002-02-07

Applicant: IBM

Inventor： ACOSTA RAUL ,  LUND JENNIFER ,  GROVES ROBERT ,  ROSNER JOANNA ,  CORDES STEVEN ,  CARASSO MELANIE

IPC: H01F17/00 ,  H01F41/04 ,  H01F17/02 ,  H01F27/36

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

公开(公告)号：PL347361A1

公开(公告)日：2002-04-08

申请号：PL34736199

申请日：1999-10-27

Applicant: IBM

Inventor： GROVES ROBERT ,  JADUS DALE ,  NGUYEN-NGOC DOMINIQUE ,  WALER KEITH

IPC: H01L21/768 ,  H01L21/8222 ,  H01L27/082 ,  H01L21/331 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

公开(公告)号：AT463828T

公开(公告)日：2010-04-15

申请号：AT02711020

申请日：2002-02-07

Applicant: IBM

Inventor： ACOSTA RAUL ,  LUND JENNIFER ,  GROVES ROBERT ,  ROSNER JOANNA ,  CORDES STEVEN ,  CARASSO MELANIE

IPC: H01F17/00 ,  H01F41/04 ,  H01F17/02 ,  H01F27/36

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

公开(公告)号：CA2434875A1

公开(公告)日：2002-07-25

申请号：CA2434875

申请日：2002-01-11

Applicant: IBM

Inventor： STAMPER ANTHONY ,  RICE MICHAEL ,  NAKOS JAMES ,  GROVES ROBERT ,  BALLANTINE ARNE ,  LUND JENNIFER

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery (420) within an integrated circuit for providing voltage to low-current electronic devices (900) that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices (900) on a semiconductor wafer (402), followed by Back-End-Of-Line (BEOL) integration f or wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery (420) is formed during BEOL integration within one or more wiring levels, and the conductive metallization (432,434,442,444) conductively couples positive (42 4) and negative (422) terminals of the battery to the electronic devices (900). The battery (420) may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：AT384685T

公开(公告)日：2008-02-15

申请号：AT02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD ,  BISSON JOHN ,  COTE DONNA R ,  DALTON TIMOTHY ,  GROVES ROBERT ,  PETRARCA KEVIN ,  STEIN KENNETH ,  SUBBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H49/00 ,  H01H59/00

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：GB2399451B

公开(公告)日：2005-08-17

申请号：GB0318083

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE ,  GROVES ROBERT ,  LUND JENNIFER ,  NAKOS JAMES ,  RICE MICHAEL ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：CZ20011568A3

公开(公告)日：2001-11-14

申请号：CZ20011568

申请日：1999-10-27

Applicant: IBM

Inventor： GROVES ROBERT ,  JADUS DALE ,  NGUYER-NGOC DOMINIQUE ,  WALER KEITH

IPC: H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

公开(公告)号：AT478438T

公开(公告)日：2010-09-15

申请号：AT02725187

申请日：2002-03-13

Applicant: IBM

Inventor： ACOSTA RAUL ,  CARASSO MELANIE ,  CORDES STEVEN ,  GROVES ROBERT ,  LUND JENNIFER ,  ROSNER JOANNA

IPC: H01L29/82 ,  H01F17/00 ,  H01F17/04 ,  H01F17/06 ,  H01F27/00 ,  H01F27/06 ,  H01F41/04 ,  H01L21/02 ,  H01L27/08 ,  H01L29/00

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

公开(公告)号：GB2399451A

公开(公告)日：2004-09-15

申请号：GB0318083

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE ,  GROVES ROBERT ,  LUND JENNIFER ,  NAKOS JAMES ,  RICE MICHAEL ,  STAMPER ANTHONY

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A method and structure that provides a battery (420) within an integrated circuit for providing voltage to low-current electronic devices (900) that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices (900) on a semiconductor wafer (402), followed by Back-End-Of-Line (BEOL) integration for wires the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery (420) is formed during BEOL integration within one or more wiring levels, and the conductive metallization (432,434,442,444) conductively couples positive (424) and negative (422) terminals of the battery to the electronic devices (900). The battery (420) may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

公开(公告)号：HU0104030A2

公开(公告)日：2002-03-28

申请号：HU0104030

申请日：1999-10-27

Applicant: IBM

Inventor： GROVES ROBERT ,  JADUS DALE ,  NGUYEN-NGOC DOMINIQUE ,  WALER KEITH

IPC: H01L21/768 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.