Abstract:
System für eine Kombinations-Fehler- und Löschdecodierung für Produktcodes, wobei das System einen Prozessor und Logik aufweist, die in den Prozessor integriert und/oder von dem Prozessor ausführbar ist, wobei die Logik so konfiguriert ist, dass sie:erfasste Daten empfängt (402, 602);Löschmarkierungen für die erfassten Daten erzeugt (404, 604) und die Löschmarkierungen einem C2-Decodierer bereitstellt;einen Stopp-Parameter so setzt (406, 606), dass er einer Länge von C1-Codewörtern in einer Codewort-Verschachtelung entspricht, die zur Codierung der erfassten Daten verwendet werden; undin einem iterativen Prozess (408, 608) eine Fehler- oder Lösch-C1-Decodierung, gefolgt von einer Fehler- oder Lösch-C2-Decodierung selektiv durchführt, bis eines von zumindest zwei Fehlerkriterien, nämlich das erste Fehlerkriterium „Decodierung erfolgreich“ (416, 424) oder das zweite Fehlerkriterium „Decodierung nicht erfolgreich“ (428) erfüllt ist.
Abstract:
In einer Ausführungsform enthält ein System einen Controller und eine Logik, die in den Controller integriert und/oder von diesem ausführbar ist. Die Logik ist zum Ausführen einer iterativen Decodierung von verschlüsselten Daten konfiguriert, um entschlüsselte Daten zu erhalten. In der iterativen Decodierung werden mindestens drei Decodierungsoperationen ausgeführt, wobei die Decodierungsoperationen aus einer Gruppe ausgewählt werden, aufweisend: C1-Decodierung und C2-Decodierung. Die Logik ist außerdem zum Ausführen einer der Decodierung nachfolgenden Fehlerdiagnose an einem ersten Abschnitt der entschlüsselten Daten konfiguriert in Reaktion darauf, dass nach der iterativen Decodierung der verschlüsselten Daten kein gültiges Produktcodewort in dem ersten Abschnitt erhalten wurde. Weitere Systeme, Verfahren und Computerprogrammprodukte zum Erzeugen von einer Decodierung nachfolgenden Fehlersignaturen werden gemäß weiteren Ausführungsformen vorgestellt.
Abstract:
In einer Ausführungsform enthält ein System eine Logik, die konfiguriert ist, um zu veranlassen, dass Daten, die in eine Mehrzahl von logischen Arrays mit Zeilen und Spalten mit Symbolen organisiert sind, in einen ersten Schreibabschnitt eines Magnetdatenträgers als eine Mehrzahl von CWI-4-Gruppen geschrieben werden, wobei jede Zeile der logischen Arrays vier verschachtelte C1'-Codewörter mit Header (eine CWI-4 mit Header) enthält, wobei jede CWI-4-Gruppe M gleichzeitig geschriebene Zeilen eines logischen Arrays mit M entsprechenden ersten Headern enthält und veranlasst, dass einige der Daten in einen Umschreibabschnitt des Magnetdatenträgers als eine oder mehrere umgeschriebene CWI-4-Gruppen geschrieben werden, wobei eine Länge von mindestens einer umgeschriebenen Zeile größer ist als mindestens eine von: einer Länge einer anderen umgeschriebenen Zeile in derselben umgeschriebenen CWI-4-Gruppe und einer Länge von mindestens einer Zeile in einer CWI-4-Gruppe, die in dem ersten Schreibabschnitt des Magnetdatenträgers gespeichert ist.
Abstract:
A method for randomizing data to mitigate false VFO detection is described. In one embodiment, such a method includes simultaneously receiving multiple input data streams. Each input data stream is associated with a different track on a magnetic tape medium. The input data streams are simultaneously scrambled to produce multiple randomized data streams. The input data streams are scrambled such that different bit patterns are produced in the randomized data streams even where corresponding bit patterns in the input data streams are identical. The randomized data streams are simultaneously written to their associated data tracks on the magnetic tape medium.
Abstract:
A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.
Abstract:
PROBLEM TO BE SOLVED: To provide a memory access device for sharing a buffer for data flows of an information device and a main memory for a processor. SOLUTION: An arbiter unit assigns access requests to the memory from a plurality of functional blocks sequentially by a round-robin method with a predetermined transfer length. (a) Data transfer from a functional block is split into partial transfers by a predetermined transfer length, and a plurality of partial transfers are performed according to a band for data transfer in one round-robin cycle. (b) The plurality of partial transfers have different priorities, and the priorities are programmably set up so that the required band of data transfer from all functional blocks may be satisfied by alternate transfer of the partial transfers from different functional blocks. (c) An access from the processor is executed so that the number of accesses from the processor to the memory may exert less effect on bands for data flow transfers with top priority and with a predetermined transfer length (CPU transfer length) in predetermined intervals between the transfer blocks. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To accelerate reading out of a specific kind of data from among a plurality of kinds of data with different formats. SOLUTION: In a controller 16 of a tape drive, a command processing unit 41 receives a request for reading out old data behind EOD of new data; a channel input/output unit 43 receives data read out with a read head in response to the request; and a buffer managing unit 42 receives this data. A header information determining unit 44 determines whether this data includes header information of the old data. If it is determined that this data includes the header information of the old data, a data set determining unit 45 determines whether a data set is extractable from this data. If it is determined that the data set is not extractable, a move signal output unit 47 outputs a signal for moving the read head in a direction of the new data. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To shorten the total processing time needed for correction of errors by taking out two position data adjacent to each other in a single line that is sorted as an erased line and also two information data related to the position data and then repetitively correcting two position data based on the patterns included in those position and information data until all lines are corrected. SOLUTION: The coding data on a row 1 included in every group which are stored in the memory sections 14 and 15 and taken out of a main memory 12 are sent to a wrong data position/pattern generator 16 via a line 24. Thus, the information blocks are generated. The generator 16 detects via an erased line pointer of a register 32 whether the wrong data under processing belong to an erased line or non-erased line. Then generator 16 calculates the wrong data position of the erased line to generate an information block, including a bit pattern that corrects the wrong data position and sends the information block to a memory section 14A of a buffer memory 13 to assemble the rows. It is checked whether all rows have been processed, and these operations are repeated until all the rows are have been corrected.
Abstract:
PROBLEM TO BE SOLVED: To improve the operating efficiency of a working memory by setting two memory banks having a specific total byte length, dividing them into specific blocks having a specific by te length and dividing plural encoded data rows which are to be read out in series from a recording disk into specific byte lengths and specific blocks which are to be set in the memory banks and storing the specific blocks alternately. SOLUTION: In the case of reading out plural encoded data having a Y byte length, the right-hand side 2 ×(2m+1)of Y ×(2m+1) is divided into (2m+1) pieces of blocks and the length of each block is set to a 2 byte length, Then, in an encoded data row L01 or L04, the first block and the second block of the encoded data row L01 are respectively stored in the block A0 of a memory bank 0 and the block B0 of a memory bank 1 under the control of a buffer manager. The error correction of the encoded data row L01 is performed by taking out the block A0 of the bank 0, the block B0 of the bank 1 and the block A1 of the bank 0 alternately.
Abstract:
PROBLEM TO BE SOLVED: To reduce the consumption of memory resources through a single processing route by identifying first and second channel bits, removing a pattern not present on a first PLL rule from the patterns of first channel bit display, generating an output bit and removing the pattern not present in a second PLL rule from the patterns of second channel bit display. SOLUTION: The 8/16 modulated or EFM modulated channel bits of 16 bits or 14 bits are inputted through an input line to the data input of a buffer register 500, and the data of the channel bits are stored for 8 bits in a higher order and for 8 or 6 bits in a lower order by loading control from an arithmetic control circuit 550. The data of the upper 8 bits of the buffer register 500 are sent to a demultiplexer 501, and for medium information from an arithmetic circuit 550, the data of the lower 8 bits are sent to an 8/16 bit operation I circuit 511 at the time of a DVD and the lower 6 bits are sent to a bit operation III circuit 530 at a CD time.