公开(公告)号：JPH04148590A

公开(公告)日：1992-05-21

申请号：JP25546490

申请日：1990-09-27

Applicant: IBM

Inventor： TSUKADA YUTAKA ,  TSUCHIDA SHUHEI

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/18 ,  H05K3/42 ,  H05K3/46

Abstract: PURPOSE: To enhance wiring density and degrees of freedom in wiring layout and to minimize through-hole connections by using one side of a both-side copper coated circuit board for mounting parts and supplying a ground potential, and using the other side for supplying a power supply voltage. CONSTITUTION: A glass epoxy insulating board 10, of which both the sides are coated with copper layers 12 and 14, is prepared. A copper layer 12 is patterned by selective etching, so as to form a 1st wiring layer or wiring level including a signal wiring conductor 16. The downside copper layer 14 is used as a power supply layer. A photosensitive resin insulating layer 18 is applied, so as to cover the signal wiring conductor 16 on the 1st wiring layer, the photosensitive resin insulating layer 18 is exposed and developed, and a via 20 is formed at a selected position. All the surface of the insulating layer 18 forming the via 20 is coated with copper by non-electric plating, and a copper layer 22 at a 2nd level is formed. The copper layer 22 at the 2nd level is connected to the signal wiring conductor 16 at a 1st level by a plated via 24.

公开(公告)号：JP2004158703A

公开(公告)日：2004-06-03

申请号：JP2002324098

申请日：2002-11-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MORI HIROYUKI ,  TSUKADA YUTAKA

IPC: H05K3/42 ,  H05K3/46

CPC classification number: H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0353

Abstract: PROBLEM TO BE SOLVED: To reduce electric connection failure between conductive layers generated due to the thermal expansion difference of an insulating layer and a conductor layer in the via hole of a printed wiring board. SOLUTION: In this printed wiring board, the area of a joint face 18 of a first conductor 12 and a second conductor 15 at a via bottom part, and the second conductor 15 is provided with a fringe(collar) area 21 connected to a surface 17 of the second insulating layer at an outer peripheral part 20 of the opening of the second insulating layer 14 at the via bottom part. Therefore, the printed wiring board can be stabilized against a tensile stress generated due to the thermal expansion difference of the insulating layer and the conductor layer, and any electric connection failure between the conductor layers in the via can be prevented from being generated. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003007894A

公开(公告)日：2003-01-10

申请号：JP2001176650

申请日：2001-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： YAMANAKA KIMIHIRO ,  TSUKADA YUTAKA

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/12 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/041 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a ball grid array module in which there is no loss of solder ball in a ball grid array even if locating the solder ball and making a treatment of reflow, etc.
SOLUTION: The ball grid array module includes a substrate, which has a surface for mounting a semiconductor chip and the solder ball and which has at least two layers of electric construction containing a circuit on a the solder ball mounting surface, and a plurality of space portions 18, which is located to mount a solder ball 29 on the solder ball mounting surface. Each of the space portions 18 is formed in a part of the inside of the electric construction, an opening portion of the space portion 18 is provided in a solder resist layer 16 which is an outermost layer of the solder ball mounting surface.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种球栅阵列模块，其中即使定位焊球并对回流焊等进行处理也不会在球栅阵列中失去焊球。解决方案：球栅阵列模块包括： 基板，其具有用于安装半导体芯片的表面和焊球，并且其具有在焊球安装表面上包含电路的至少两层电气结构，以及多个空间部分18，其位于安装 焊球29上的焊球安装面。 每个空间部分18形成在电气结构的内部的一部分中，空间部分18的开口部分设置在作为焊球安装表面的最外层的阻焊层16中。

公开(公告)号：JP2002093853A

公开(公告)日：2002-03-29

申请号：JP2000271237

申请日：2000-09-07

Applicant: IBM

Inventor： MORI HIROYUKI ,  YAMANAKA KIMIHIRO ,  TSUKADA YUTAKA

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board for mounting thereon a semiconductor chip and to provide a method for flip-chip bonding the semiconductor chip to the printed wiring board. SOLUTION: A printed wiring board 1 for flip-chip bonding thereto a semiconductor chip 7, includes each circuit pattern 6a connected with each conductive protrusion 8 provided in each corner portion of the semiconductor chip 7 and an insulation layer 3a for holding thereon the circuit patterns 6a. Furthermore, at each portion of the insulation layer 3a which is present near each circuit pattern 6a connected with each conductive protrusion 8, each protective pad 9 corresponding to each corner portion of the semiconductor chip 7 is formed.

公开(公告)号：JPH05251516A

公开(公告)日：1993-09-28

申请号：JP34482291

申请日：1991-12-26

Applicant: IBM

Inventor： TSUKADA YUTAKA

IPC: H01L21/56 ,  H01L21/60

Abstract: PURPOSE: To easily exchange a facedown bonded resin-sealed semiconductor chip, without lowering reliability. CONSTITUTION: A facedown bonded semiconductor chip 4, which is sealed with resin 14, is cut by a cutting end mill and removed from a substrate 2. Then the resin 14 and a bump electrode 16 left on the substrate 2 are ground by a finishing end mill to nearly a half as large as the original height and are thus flattened. Another chip 4A with a bump electrode 6A is positioned at a bump electrode 6 on the substrate 2 and bonded facedown. Lastly, resin 14A is supplied to the gap between the chip 4A and substrate 2 and the circumference of the chip 4A to be sealed.

公开(公告)号：JP2004335655A

公开(公告)日：2004-11-25

申请号：JP2003128155

申请日：2003-05-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YASUDA MASAHARU ,  YAMANAKA KIMIHIRO ,  TSUKADA YUTAKA

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/42 ,  H05K1/02 ,  H05K3/00 ,  H05K3/42

Abstract: PROBLEM TO BE SOLVED: To provide a hole forming method for drilling a substantially straight hole on a board, a printed wiring board having a hole formed by this method, and a hole forming device for forming the hole. SOLUTION: The printed wiring board 10 is irradiated with a laser 24 from its front surface to form a halfway hole 18a, and the board 10 is irradiated with the laser 24 from its rear surface to form a penetrated hole 18. Since the hole 18 is formed by irradiating the board 10 with the laser 24 from its both surfaces, the substantially straight hole 18 can be formed, and a plating liquid can smoothly flow inside the hole 18. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2001102749A

公开(公告)日：2001-04-13

申请号：JP26468499

申请日：1999-09-17

Applicant: IBM ,  NGK INSULATORS LTD

Inventor： TERADA KENJI ,  TSUKADA YUTAKA ,  SUZUKI TOMIO ,  ODAGIRI TADASHI

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a circuit board formed to enhance reliability of three- dimensionally laid conductors, so that vias and buildup layer are not stressed by deformation due to the thermal expansion difference between the metal of the vias and an insulating material. SOLUTION: This circuit board 3 is composed of a base board 4, having a metal embedded at specified pitches as vias 20 into an insulating material which contains an epoxy resin and amorphous silica as main components and has an isotropic thermal expansion coefficient, and at least one of insulation layers and one of conductor layers laminated alternately on the base board 4.

公开(公告)号：JP2000294584A

公开(公告)日：2000-10-20

申请号：JP9237499

申请日：1999-03-31

Applicant: IBM

Inventor： MAEDA YOJI ,  TSUKADA YUTAKA

IPC: H01L21/60 ,  B23K3/06 ,  B23K35/14 ,  H01L21/48 ,  H05K3/34 ,  B05C3/09 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To form a bump of a proper size without requiring almost any adjustment operation regardless of density and a pattern of a pad whereon a bump is formed by fixing molten solder to a pad by moving a frame wherein molten solder is put relatively in parallel to a flat surface with a pad. SOLUTION: A formation device 10 wherein a formation member 16 and a container 14 are incorporated integrally is constituted to be supported by a supporting member 38, for example, and is moved in parallel to a substrate 24 by a movement means. A roller 42 is moved by a movement means along a surface 40 of the supporting member 38, and the formation device 10 is moved in parallel to the substrate 24. A solder bump 44 can be formed in a pad 22 on the substrate 24 by extruding molten solder 12 from the container 14 into a chamber 26 of the molding member 16.

公开(公告)号：JPH0951168A

公开(公告)日：1997-02-18

申请号：JP20198595

申请日：1995-08-08

Applicant: IBM

Inventor： SHIRAI MASAHARU ,  TSUKADA YUTAKA

IPC: G03F7/11 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To suppress the migration of a conductor layer in a multilayer printed circuit board without changing a prior art manufacturing process or structure largely. SOLUTION: A photosetting layer 13, being a migration resisting layer, is formed between insulating layers 12a, 12b located between a conductor layer 8, being a first layer, and a conductor layer 6, being a second layer, to improve migration resistance in z direction. Such a structure can be manufactured by grinding the photosetting layer and a part of the insulating layers to such an extent that about half of the designed thickness of the insulating layers is left, and then forming a via-hole in a predetermined pattern after obtaining a hardened layer by once irradiating the surface of the insulating layer with light, and further again spreading and grinding an insulating layer and forming a via-hole at the same place.

公开(公告)号：JPH08148566A

公开(公告)日：1996-06-07

申请号：JP28811494

申请日：1994-11-22

Applicant: IBM

Inventor： SHIRAI MASAHARU ,  TERADA KENJI ,  TSUKADA YUTAKA ,  TSUCHIDA SHUHEI

IPC: H01L21/28 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H05K3/00 ,  H05K3/46

Abstract: PURPOSE: To provide a method of manufacturing a semiconductor device proper to form a via hole for easily attaching a conductor layer uniformly to the via hole in a substantially bowl shape. CONSTITUTION: A photosensitive resin 3 is mounted on a substrate 1 so that thickness, in which the thickness is removed by the grinding of the photosensitive resin 3 in a post-process is added to final required thickness as an insulating layer, is obtained. A cavity is formed to the photosensitive resin 3 by a specified pattern by exposure, development and etching, and the photosensitive resin 3, to which the cavity if formed, is thermoset. When a photosetting layer 6a show by a dotted line and a part of a thermosetting layer 3a in Fig. are ground and removed, a via hole 9 having a substantially bowl shape is formed.