公开(公告)号：EP1653789A4

公开(公告)日：2008-09-24

申请号：EP04746998

申请日：2004-07-05

Applicant: IBM

Inventor： MORI HIROYUKI ,  YAMANAKA KIMIHIRO ,  KODAMA YASUSHI

IPC: H05K3/46 ,  H05K1/03 ,  H05K3/42

CPC classification number: H05K3/421 ,  H05K1/0366 ,  H05K3/4644 ,  H05K2201/029 ,  H05K2201/0769 ,  H05K2201/09509 ,  H05K2201/09581 ,  Y10T29/49155

Abstract: A printed-wiring board capable of preventing occurrence of short-circuit is provided. A printed-wiring board (100) comprises a via land (2A), a glass epoxy resin layer (3), a via conductor (6), and a block layer (4A). The via land (2A) is formed on a core layer (1). The glass epoxy resin layer (3) is formed on the core layer (1) and via land (2A). The via conductor (6) is formed on the via land (2A). The block layer (4A) is formed on the via land (2A) and between the via conductor (6) and glass epoxy resin layer (3).

公开(公告)号：DE112020004630T5

公开(公告)日：2022-06-09

申请号：DE112020004630

申请日：2020-08-19

Applicant: IBM

Inventor： MIYAZAWA RISA ,  WATANABE TAKAHITO ,  MORI HIROYUKI ,  OKAMOTO KEISHI

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

Abstract: Es wird ein Verfahren zum Herstellen einer Verbindungsstruktur offenbart. Das Verfahren weist ein Bereitstellen eines Substrats auf, das eine obere Oberfläche aufweist und einen Satz von Kontaktstellen für einen Lötvorgang aufweist, die jeweils eine Kontaktstellenoberfläche aufweisen, die in Bezug auf die obere Oberfläche des Substrats freiliegt. Das Verfahren weist außerdem ein Anwenden einer Oberflächenbehandlung auf einen Teil der oberen Oberfläche des Substrats nahe bei den Kontaktstellen und auf die Kontaktstellenoberfläche jeder Kontaktstelle auf, um so zumindest dem Teil der oberen Oberfläche und den Kontaktstellenoberflächen der Kontaktstellen eine größere Rauigkeit zu verleihen.

公开(公告)号：DE112018003103T5

公开(公告)日：2020-03-26

申请号：DE112018003103

申请日：2018-08-01

Applicant: IBM

Inventor： OKAMOTO KEISHI ,  HORIBE AKIHIRO ,  MORI HIROYUKI

IPC: H05K3/06

Abstract: Eine Technik zum Verbinden von Chips mithilfe eines Verbindungssubstrats wird offenbart. Das Verbindungssubstrat enthält ein Basissubstrat, eine erste Gruppe von Elektroden auf dem Basissubstrat für einen ersten zu montierenden Chip und eine zweite Gruppe von Elektroden auf dem Basissubstrat für einen zweiten zu montierenden Chip. Das Verbindungssubstrat enthält des Weiteren eine Verbindungsschicht, die einen ersten Satz von Kontaktflächen für den ersten Chip, einen zweiten Satz von Kontaktflächen für den zweiten Chip, Leiterbahnen und ein organisches Isolationsmaterial enthält. Die Verbindungsschicht ist auf dem Basissubstrat angeordnet und befindet sich innerhalb eines definierten Bereichs auf dem Basissubstrat zwischen der ersten Gruppe von Elektroden und der zweiten Gruppe der Elektroden.

公开(公告)号：DE112020004638T5

公开(公告)日：2022-06-09

申请号：DE112020004638

申请日：2020-08-26

Applicant: IBM

Inventor： MIYAZAWA RISA ,  WATANABE TAKAHITO ,  MORI HIROYUKI ,  OKAMOTO KEISHI

IPC: H01L23/498 ,  H01L21/58 ,  H01L21/60 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065

Abstract: Es ist eine Zwischenverbindungsstruktur offenbart. Die Zwischenverbindungsstruktur weist ein Basis-Substrat, einen Satz von leitfähigen Kontaktstellen, die auf dem Basis-Substrat angeordnet sind, sowie eine Zwischenverbindungsschicht auf, die auf dem Basis-Substrat angeordnet ist. Die Zwischenverbindungsschicht weist einen Rand auf, der sich neben dem Satz der leitfähigen Kontaktstellen befindet, und weist einen Satz von seitlichen Verbindungskontaktstellen auf, die sich an dem Rand der Zwischenverbindungsschicht befinden und an diesem angeordnet sind. Jede seitliche Verbindungskontaktstelle ist in Bezug auf eine entsprechende der auf dem Basis-Substrat angeordneten leitfähigen Kontaktstellen angeordnet.

公开(公告)号：DE10393589T5

公开(公告)日：2005-12-22

申请号：DE10393589

申请日：2003-11-05

Applicant: IBM

Inventor： MORI HIROYUKI ,  TSUKADA YUTAKA

IPC: H05K3/42 ,  H05K3/46

Abstract: A defective electrical connection between conductor layers due to difference in thermal expansion between an insulating layer and the conductor layer is eliminated in the via hole in a printed wiring board Since the bonding face (18) between a first conductor (12) and a second conductor (15) has a large area on the bottom of a via, and the second conductor (15) has a fringe (flange) region (21) being boded to the surface (17) of a second insulating layer (14) at the outer circumferential part (20) of an opening in the second insulating layer on the bottom of the via, the printed wiring board is stabilized against a tensile stress resulting from a difference in thermal expansion between the insulating layer and the conductor layer and thereby a defective electrical connection between the conductor layers is eliminated in the via hole.

公开(公告)号：AU2003277566A1

公开(公告)日：2004-06-07

申请号：AU2003277566

申请日：2003-11-05

Applicant: IBM

Inventor： TSUKADA YUTAKA ,  MORI HIROYUKI

IPC: H05K3/42 ,  H05K3/46

Abstract: A defective electrical connection between conductor layers due to difference in thermal expansion between an insulating layer and the conductor layer is eliminated in the via hole in a printed wiring board Since the bonding face (18) between a first conductor (12) and a second conductor (15) has a large area on the bottom of a via, and the second conductor (15) has a fringe (flange) region (21) being boded to the surface (17) of a second insulating layer (14) at the outer circumferential part (20) of an opening in the second insulating layer on the bottom of the via, the printed wiring board is stabilized against a tensile stress resulting from a difference in thermal expansion between the insulating layer and the conductor layer and thereby a defective electrical connection between the conductor layers is eliminated in the via hole.

公开(公告)号：JP2010103187A

公开(公告)日：2010-05-06

申请号：JP2008271265

申请日：2008-10-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MORI HIROYUKI ,  KAWASAKI KAZUSHIGE

IPC: H01L23/12 ,  H01L21/60 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/205 ,  H05K3/421 ,  H05K3/4682 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/0574 ,  Y10T29/49124 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board that hardly generates solder bump breakage of a mounted semiconductor chip. SOLUTION: A coreless substrate 20, which is a kind of a printed wiring board, includes an insulating layer 26a having a main surface, and a connection pad 24 buried in the insulating layer 26a. The connection pad 24 includes a hat-like shape. That is, the connection pad 24 consists of a plate part 36 with a diameter ϕ1 of about 95 μm, and a contact part 38 with a diameter ϕc of 75 μm. A main surface 39 of the contact part 38 is exposed in the main surface 7 of the insulating layer 26a. Since the diameter ϕc of the contact part 38 is substantially the same as a diameter ϕ2 of an under bump metal 11 on the semiconductor chip 8 side, when mechanical stress is added in a direction in which the semiconductor chip 8 is peeled from the coreless substrate 20, the stress is equally dispersed to both sides of the connection pad 24 and the under bump metal 11, and as a result, it is hard to generate breakage. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供几乎不产生安装的半导体芯片的焊料破损的印刷线路板。 解决方案：作为一种印刷电路板的无芯基板20包括具有主表面的绝缘层26a和埋在绝缘层26a中的连接焊盘24。 连接垫24包括帽状。 也就是说，连接垫24由直径φ1为约95μm的板部36和直径φc为75μm的接触部38组成。 接触部分38的主表面39暴露在绝缘层26a的主表面7中。 由于接触部38的直径φc与半导体芯片8侧的下凸块状金属11的直径φ2基本相同，所以当在从无芯基板剥离半导体芯片8的方向上添加机械应力时 如图20所示，应力均等地分散在连接焊盘24和下凸块金属11的两侧，结果难以产生断裂。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007180384A

公开(公告)日：2007-07-12

申请号：JP2005378948

申请日：2005-12-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YAMAJI YOSHIYUKI ,  NOMAN YUICHI ,  MORI HIROYUKI

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package which has superior high-frequency characteristics and can increase the area of an internal wiring pattern. SOLUTION: The semiconductor package is equipped with a multilayer printed wiring board 12, an IC chip mounted on its surface, and a plurality of bump terminals 16 mounted on the reverse surface of the multilayer printed wiring board 12. Each of the bump terminals 16 includes an insulating core 42 having a plane 40, and a conductive film 44 formed on a surface other than the plane 40. The end surface of the conductive film 44 appears annularly at the circumference of the insulating core 42, and is soldered to an annular connection pad 52 formed on the reverse surface of the multilayer printed wiring board 12. A via hole 36 is formed right above the bump terminal 16, and a clearance hole 34 that the via hole 36 runs through is formed in internal wiring patterns 28 and 30. The diameter of the clearance hole 34 is made smaller than the diameter of the bump terminal 16. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有优异的高频特性并且可以增加内部布线图案的面积的半导体封装。 解决方案：半导体封装配备有多层印刷线路板12，安装在其表面上的IC芯片和安装在多层印刷线路板12的背面上的多个凸点端子16.每个凸起 端子16包括具有平面40的绝缘芯42和形成在除了平面40之外的表面上的导电膜44.导电膜44的端表面环形地出现在绝缘芯42的圆周处，并被焊接到 形成在多层印刷布线板12的背面上的环形连接焊盘52.在凸块端子16正上方形成有通孔36，通孔36穿过的间隙孔34形成在内部布线图形28中 间隙孔34的直径小于凸块端子16的直径。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：JP2004158703A

公开(公告)日：2004-06-03

申请号：JP2002324098

申请日：2002-11-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MORI HIROYUKI ,  TSUKADA YUTAKA

IPC: H05K3/42 ,  H05K3/46

CPC classification number: H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0353

Abstract: PROBLEM TO BE SOLVED: To reduce electric connection failure between conductive layers generated due to the thermal expansion difference of an insulating layer and a conductor layer in the via hole of a printed wiring board. SOLUTION: In this printed wiring board, the area of a joint face 18 of a first conductor 12 and a second conductor 15 at a via bottom part, and the second conductor 15 is provided with a fringe(collar) area 21 connected to a surface 17 of the second insulating layer at an outer peripheral part 20 of the opening of the second insulating layer 14 at the via bottom part. Therefore, the printed wiring board can be stabilized against a tensile stress generated due to the thermal expansion difference of the insulating layer and the conductor layer, and any electric connection failure between the conductor layers in the via can be prevented from being generated. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002093853A

公开(公告)日：2002-03-29

申请号：JP2000271237

申请日：2000-09-07

Applicant: IBM

Inventor： MORI HIROYUKI ,  YAMANAKA KIMIHIRO ,  TSUKADA YUTAKA

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board for mounting thereon a semiconductor chip and to provide a method for flip-chip bonding the semiconductor chip to the printed wiring board. SOLUTION: A printed wiring board 1 for flip-chip bonding thereto a semiconductor chip 7, includes each circuit pattern 6a connected with each conductive protrusion 8 provided in each corner portion of the semiconductor chip 7 and an insulation layer 3a for holding thereon the circuit patterns 6a. Furthermore, at each portion of the insulation layer 3a which is present near each circuit pattern 6a connected with each conductive protrusion 8, each protective pad 9 corresponding to each corner portion of the semiconductor chip 7 is formed.