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    HIGHLY INTEGRATED, HIGH-SPEED MEMORY WITH BIPOLAR TRANSISTORS
    14.
    发明专利
    HIGHLY INTEGRATED, HIGH-SPEED MEMORY WITH BIPOLAR TRANSISTORS 未知

    公开(公告)号：CA1182218A

    公开(公告)日：1985-02-05

    申请号：CA398572

    申请日：1982-03-17

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: G11C11/411 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/082 ,  H01L27/102 ,  G11C7/00 ,  G11C11/40

    Abstract: HIGHLY INTEGRATED HIGH-SPEED MEMORY WITH BIPOLAR TRANSISTORS A memory is described comprising a static MTL memory cell for high speeds, wherein the cell or primary injectors (Pl, Pl') and the bit line injectors (P4 and P5) are coupled to each other by angular injection coupling via the low-resistivity base region of the flip-flop transistors (T2 and T3) of the memory cell. Such a memory cell has a structure with a low-resistivity signal path in the current flow area. The density is additionally increased by the primary injectors and the bit line injectors of adjacent cells of the array being used in common several times at a very high read signal.

    BI-POLAR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FABRICATING SAME
    15.
    发明专利
    BI-POLAR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FABRICATING SAME 未知

    公开(公告)号：CA1092722A

    公开(公告)日：1980-12-30

    申请号：CA287816

    申请日：1977-09-29

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H01L27/04 ,  H03K19/08

    Abstract: An integrated logic circuit is formed on a layer of semi-con-ductive material of one conductive type. The first region of the opposite conductivity type is formed in the layer with no contact means formed on or in it so that no external electrical signals can be applied to the first region. A second region of the one conductivity type is formed within the first region and provides, with the first region and the layer, a vertical transistor structure. Third and fourth regions of the opposite conductivity type are formed in the layer at positions spaced away from each other and from the first region so that the layer forms the base region of both a first lateral transistor comprising the fourth and third regions, and of a second lateral transistor comprising the third and first regions. Means operable to inject current into the layer performed in the base region of both lateral transistors through the fourth region. An input circuit for applying input voltage signals to the third region to control the current distribution between the two lateral transistors and thus the current supplied to the first region is formed in the base region of the vertical transistor. An output circuit comprises the controlled current path of the vertical transistor. the vertical transistor is normally operated so that the second region acts as the collector zone. One or more further regions of the opposite conductivity type may be formed in the layer at positions spaced away from each other and from the first, third and fourth regions. Each further region has an individual further input circuit whereby a pattern of input voltage signals applied simultaneously to the third and further regions determines the base currents applying to the base of the vertical transistor.

    MTL (MERGED TRANSISTOR LOGIC) OR I2L (INTEGRATED INJECTION LOGIC) CIRCUITRY
    16.
    发明专利
    MTL (MERGED TRANSISTOR LOGIC) OR I2L (INTEGRATED INJECTION LOGIC) CIRCUITRY 未知

    公开(公告)号：CA1079819A

    公开(公告)日：1980-06-17

    申请号：CA247403

    申请日：1976-03-05

    Applicant: IBM

    Inventor： BERGER HORST H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/73 ,  H03K19/091 ,  H01L27/04 ,  H03K19/08 ,  H03K19/36

    Abstract: MTL (MERGED TRANSISTOR LOGIC) OR I2L (INTEGRATED INJECTION LOGIC) CIRCUITRY The disclosure is directed to Merged Transistor Logic (MTL) circuitry or Integrated Injection Logic (I2L) circuitry. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multi-collector inverter transistors which are fed by means of a carrier injection into their emitter/base zones. Binary inputs are provided to the integrated logic circuitry and combined logically within the circuitry to provide a combined logical output. The circuitry consists of a plurality of transistors of both a first and second conductivity type having input terminals and common connection means to a plurality of output terminal representative of the logical output.

    17.
    发明专利
    未知

    公开(公告)号：FR2401489A1

    公开(公告)日：1979-03-23

    申请号：FR7821335

    申请日：1978-07-12

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: G11C11/411 ,  H01L27/102 ,  H03K3/288 ,  G11C11/34 ,  H01L27/06

    Abstract: The invention relates to a monolithically integrated storage cell which includes a flip-flop circuit with two cross-coupled, bipolar switching transistors and one load element each connected by means of one terminal to the collectors of the switching transistors, the storage cell being controlled via a word line connected to the other terminal of both load elements and via one bit line each of a bit line pair connected to the emitter of each switching transistor.

    SEMICONDUCTOR MEMORY
    19.
    发明专利
    SEMICONDUCTOR MEMORY 未知

    公开(公告)号：CA1232354A

    公开(公告)日：1988-02-02

    申请号：CA477994

    申请日：1985-03-29

    Applicant: IBM

    Inventor： WIEDMANN SIEGFRIED K

    IPC: G11C11/41 ,  G11C5/02 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/14 ,  G11C11/34

    Abstract: SEMICONDUCTOR MEMORY A novel memory structure for very big memory arrays on a chip is described whose memory array is divided into a number of subarrays (SA 1 to SA N). The subarrays are controlled via common word decoders and subarray decoders (WD and DSA, respectively). The word lines of the individual subarrays are individually selectable through word line switches (WS), and the bit lines of the subarrays are applied directly to a common line system (RB and WB), and interconnected in such a manner that the peripheral circuits as e.g. the data input and output circuits (DI and DO) can be arranged in practically any free location on the chip.

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