公开(公告)号：GB2325541A

公开(公告)日：1998-11-25

申请号：GB9806453

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08

Abstract: Cache (e.g read/write) and architectural specific (e.g data move, status change) functions are layered (separated) within a cache controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable. The cache and architectural functions are handled by respective controller units 212, 214.

公开(公告)号：GB2513509B

公开(公告)日：2015-01-14

申请号：GB201414381

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/30 ,  G06F9/38

公开(公告)号：GB2500964B

公开(公告)日：2014-06-11

申请号：GB201300936

申请日：2013-01-18

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  SHEN HUGH ,  STUECHELI JEFFREY A

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0842

公开(公告)号：GB2325540A

公开(公告)日：1998-11-25

申请号：GB9806451

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08

Abstract: Cache functions (e.g. read/write) and architectural functions (e.g. data move, status change) are layered (separated) in a shared-cache controller 402 which includes controller units 404-410, 416 for different types of operations. When operations initiated by different processors compete for the use of a particular controller unit, a throttle unit serialises the operations and resolves operation flow rate issues with acceptable performance trade-offs. The layering and use of generic interfaces isolate controller logic from architectural complexities and allow controller logic to be duplicated readily so that a non-shared-cache design can be extended to a shared-cache design by straightforward modification.

公开(公告)号：DE112013000889T5

公开(公告)日：2014-10-16

申请号：DE112013000889

申请日：2013-01-23

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

IPC: G06F15/167

Abstract: Ein Mehrfachprozessor-Datenverarbeitungssystem enthält eine Vielzahl von Cachespeichern, die einen Cachespeicher enthalten. Als Reaktion auf ein Erkennen einer speichermodifizierenden Operation durch den Cachespeicher, die eine selbe Zieladresse wie diejenige einer ersten durch den Cachespeicher verarbeiteten Operation des Lesetyps angibt, stellt der Cachespeicher eine Neuversuchsantwort für die speichermodifizierende Operation bereit. Als Reaktion auf den Abschluss der Operation des Lesetyps tritt der Cachespeicher in einen Schiedsrichtermodus ein. Während er sich im Schiedsrichtermodus befindet, erhöht der Cachespeicher vorübergehend dynamisch eine Priorität irgendeiner speichermodifizierenden Operation, die auf die Zieladresse abzielt, im Verhältnis zu irgendeiner zweiten Operation des Lesetyps, die auf die Zieladresse abzielt.

公开(公告)号：SG66450A1

公开(公告)日：1999-07-20

申请号：SG1998000707

申请日：1998-04-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08 ,  G06F13/38

公开(公告)号：SG66448A1

公开(公告)日：1999-07-20

申请号：SG1998000680

申请日：1998-04-01

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/42

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

公开(公告)号：GB2325542A

公开(公告)日：1998-11-25

申请号：GB9806464

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08

Abstract: Cache and architectural-specific functions within a cache controller are layered and provided with generic interfaces, isolating the complexities of each. The functions are handled by respective controller units 212-218. This allows the overall functionality to be further divided into distinct, largely autonomous functional units. Each functional unit handles a certain type of operation and may be easily replicated or removed from the design to provide a number of cache designs with varied price and performance.

公开(公告)号：AU2013217351B2

公开(公告)日：2016-04-28

申请号：AU2013217351

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/00

Abstract: A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

公开(公告)号：GB2513509A

公开(公告)日：2014-10-29

申请号：GB201414381

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.