公开(公告)号：DE60103623T2

公开(公告)日：2005-07-21

申请号：DE60103623

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C11/4074 ,  G11C5/00

Abstract: In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.

公开(公告)号：DE60013168D1

公开(公告)日：2004-09-23

申请号：DE60013168

申请日：2000-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DANIEL GABRIEL ,  WEINFURTNER OLIVER

IPC: G11C17/14 ,  G11C17/16

Abstract: A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

公开(公告)号：DE60103623D1

公开(公告)日：2004-07-08

申请号：DE60103623

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C11/4074 ,  G11C5/00

Abstract: In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.

公开(公告)号：DE60103622D1

公开(公告)日：2004-07-08

申请号：DE60103622

申请日：2001-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C5/14 ,  G11C5/00

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

公开(公告)号：DE60103534D1

公开(公告)日：2004-07-01

申请号：DE60103534

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G05F3/24 ,  G11C5/14

Abstract: Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one "spine" section on the chip which may intersect with at least one "arm" section on the chip for supplying power from the generators, which are coupled to the power bus in the "spine" section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end. In response to such comparison, the at least one detector circuit generates control signals for transmission to the generators for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.

公开(公告)号：JP2002319282A

公开(公告)日：2002-10-31

申请号：JP2002002498

申请日：2002-01-09

Applicant: IBM

Inventor： LOUIS LU-CHEN HSU ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To provide a leak monitor element and a method improved for a DRAM. SOLUTION: A refresh-cycle time is directly adjusted based on a cell leakage state. In a method for designing a low power leakage monitor element, a memory cell being the same as a cell in an actual array is used. This monitor cell is designed so as to indicate an average cell or the worst state of cell leakage state. When leakage is severe, a refresh-cycle time is shortened greatly, for example, to a half. When a leakage level is very low or is undetectable, a refresh-cycle time is increased by a large amount for example, to twice. When leakage is normal or within a normal range, a refresh-cycle time is optimized, and power consumption used for DRAM refreshing is minimized.

公开(公告)号：WO02058072A3

公开(公告)日：2002-09-26

申请号：PCT/US0201406

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU LOUIS ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C2207/104 ,  G11C2207/2254

Abstract: A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

Abstract translation: 一种新颖的DRAM刷新方法和系统以及设计低功耗漏电监测装置的新方法。 利用DRAM刷新方法，基于单元泄漏条件来调整刷新周期时间。 设计低功率泄漏监测装置的方法使用与真实阵列中的单元相同的存储单元。 该监视器单元被设计成它将代表平均单元或最坏的单元泄漏状况。 如果泄漏严重，则刷新周期时间会显着减少或减半。 如果泄漏电平非常低或不可检测，则刷新周期时间显着增加或加倍。 如果泄漏中等或在正常范围内，则刷新时间被优化，使得用于DRAM刷新的功耗最小化。 该方法优于现有方法，即基于芯片温度调整刷新周期时间的优点包括：（1）考虑到非温度依赖性泄漏因素的贡献，（2）本发明不需要不同的 处理步骤或额外的处理成本，以及（3）本发明是一种直接的方法，监测单元不需要任何校准。 此外，其泄漏机制和可靠性问题与实际阵列中的单元格完全相同。

公开(公告)号：WO0193271A2

公开(公告)日：2001-12-06

申请号：PCT/US0117267

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU LOUIS L ,  WEINFURTNER OLIVER ,  JI BRIAN L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

CPC classification number: G11C8/08 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4078 ,  G11C2207/104

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Abstract translation: 通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。 电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。 这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。 性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

公开(公告)号：WO0133706A9

公开(公告)日：2002-07-04

申请号：PCT/US0029820

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU LOUIS L C ,  WEINFURTNER OLIVER ,  WORDEMAN MATTHEW R

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump generator system and method is provided in which on or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

Abstract translation: 提供了一种电荷泵发电机系统和方法，其中根据电压达到的电平，多个充电速率的多个电荷泵运行。 该系统包括限幅器，其基于电压电平的电平提供控制信号。 控制信号选择与其耦合的多频振荡器的频率。 选定的频率决定了用于维持电压供应的电荷泵的电荷转移速率。

公开(公告)号：DE60011471D1

公开(公告)日：2004-07-15

申请号：DE60011471

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU L ,  WEINFURTNER OLIVER ,  WORDEMAN R

IPC: H02M3/07

Abstract: A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.