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    12.
    发明专利
    未知

    公开(公告)号：DE69421071T2

    公开(公告)日：2000-04-20

    申请号：DE69421071

    申请日：1994-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B20/10

    Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

    13.
    发明专利
    未知

    公开(公告)号：DE69128987T2

    公开(公告)日：1998-06-18

    申请号：DE69128987

    申请日：1991-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

    Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

    14.
    发明专利
    未知

    公开(公告)号：IT1246467B

    公开(公告)日：1994-11-19

    申请号：IT2181690

    申请日：1990-10-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  ZUFFADA MAURIZIO ,  VAI GIANFRANCO ,  SACCHI FABRIZIO

    IPC: G06F1/24 ,  G06F7/00 ,  G06F11/00 ,  G06F11/08 ,  G06F11/28 ,  G06F11/30 ,  H03K

    Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.

    15.
    发明专利
    未知

    公开(公告)号：DE69129880D1

    公开(公告)日：1998-09-03

    申请号：DE69129880

    申请日：1991-06-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GORNATI SILVANO ,  MERLO MAURO ,  ZUFFADA MAURIZIO ,  LIETAR LOIC

    IPC: G09G1/04 ,  G09G1/12 ,  G09G1/16 ,  H04N3/27 ,  H04N5/46 ,  H03L7/18 ,  G09G1/00

    Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit (2) incorporating, a frequency meter (3) being input an analog synchronization signal (S1), a phase comparator (14) having two inputs (15,16) and in turn receiving said synchronization signal (S1) on one input (15), a voltage (Vc)-controlled oscillator (12) adapted to output a signal (S3) whose frequency is depending on said voltage (Vc) and operatively linked to an output (22) of said phase comparator (14), and a counter (9) connected with its input, on the one side, to the oscillator (12) output, and on the other side, to the meter (3) output, said counter having an output (21) connected to the other input of the phase comparator (14) also forming the integrated circuit (2) output.

    16.
    发明专利
    未知

    公开(公告)号：DE69128987D1

    公开(公告)日：1998-04-09

    申请号：DE69128987

    申请日：1991-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

    Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

    18.
    发明专利
    未知

    公开(公告)号：IT1251352B

    公开(公告)日：1995-05-08

    申请号：IT2078490

    申请日：1990-06-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GORNATI SILVANO ,  MERLO MAURO ,  ZUFFADA MAURIZIO ,  LIETAR LOIC

    IPC: G09G1/04 ,  G09G1/12 ,  G09G1/16 ,  H04N3/27 ,  H04N5/46 ,  H03B

    Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit (2) incorporating, a frequency meter (3) being input an analog synchronization signal (S1), a phase comparator (14) having two inputs (15,16) and in turn receiving said synchronization signal (S1) on one input (15), a voltage (Vc)-controlled oscillator (12) adapted to output a signal (S3) whose frequency is depending on said voltage (Vc) and operatively linked to an output (22) of said phase comparator (14), and a counter (9) connected with its input, on the one side, to the oscillator (12) output, and on the other side, to the meter (3) output, said counter having an output (21) connected to the other input of the phase comparator (14) also forming the integrated circuit (2) output.

    19.
    发明专利
    未知

    公开(公告)号：IT1250908B

    公开(公告)日：1995-04-21

    申请号：IT2072890

    申请日：1990-06-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  H01L

    Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

    20.
    发明专利
    未知

    公开(公告)号：IT9020784D0

    公开(公告)日：1990-06-27

    申请号：IT2078490

    申请日：1990-06-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GORNATI SILVANO ,  MERLO MAURO ,  ZUFFADA MAURIZIO ,  LIETAR LOIC

    IPC: G09G1/04 ,  G09G1/12 ,  G09G1/16 ,  H04N3/27 ,  H04N5/46

    Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit (2) incorporating, a frequency meter (3) being input an analog synchronization signal (S1), a phase comparator (14) having two inputs (15,16) and in turn receiving said synchronization signal (S1) on one input (15), a voltage (Vc)-controlled oscillator (12) adapted to output a signal (S3) whose frequency is depending on said voltage (Vc) and operatively linked to an output (22) of said phase comparator (14), and a counter (9) connected with its input, on the one side, to the oscillator (12) output, and on the other side, to the meter (3) output, said counter having an output (21) connected to the other input of the phase comparator (14) also forming the integrated circuit (2) output.

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