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    11.
    发明专利
    未知

    公开(公告)号：DE10333280B4

    公开(公告)日：2007-10-25

    申请号：DE10333280

    申请日：2003-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN

    IPC: G11C8/18 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    Abstract: The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s) to be accessed, accessing the corresponding memory cell or memory cells, deactivating the memory cells contained in a first set of memory cells, when one or several further memory cells that are not included in the first set of memory cells need(s) to be accessed, and prematurely deactivating the memory cells included in the first set of memory cells, when a predetermined time period or number of pulses after one or several memory cells included in the first set of memory cells have last been accessed first no further accessing of one or several of the memory cells included in the first set of memory cells takes place.

    15.
    发明专利
    未知

    公开(公告)号：DE10261409B4

    公开(公告)日：2006-05-11

    申请号：DE10261409

    申请日：2002-12-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

    IPC: H03L7/081 ,  H03K5/00 ,  H03K5/15

    Abstract: The delay locked loop includes an additional delay element (102) connected in series with a first delay element (101). A frequency detector unit (110) detects the frequency of the input signal (103). The second delay element is adjustable based on the detected frequency of the input signal. Independent claims are included for a frequency detector unit and a method of providing clock signals in circuit units.

    18.
    发明专利
    未知

    公开(公告)号：DE10230168A1

    公开(公告)日：2004-01-22

    申请号：DE10230168

    申请日：2002-07-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

    IPC: G05F5/08 ,  G11C7/10 ,  H03G3/00 ,  H03K3/356 ,  H03K5/01 ,  H03L5/00

    Abstract: The invention involves a voltage converter device ( 101 a , 101 b) for converting a signal (in) at an initial voltage level (vint) into a signal (DatoV) at a second voltage level (vint) differing from the first, in which voltage converter device ( 101 a , 101 b) has an amplifier device ( 102 ), and where the amplifier device ( 102 ) uses a second amplifier device output signal (bout) to generate signals (DatoV) at the second voltage level (vddq).

    19.
    发明专利
    未知

    公开(公告)号：DE10102000A1

    公开(公告)日：2002-08-01

    申请号：DE10102000

    申请日：2001-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

    IPC: H01L23/50 ,  H01L23/544 ,  H01L23/58

    Abstract: A description is given of an integrated circuit having components and a method for checking a connection configuration of bonding pads. The integrated circuit has an identification circuit that identifies a connection of the bonding pads to external circuits. After the identification of the connected bonding pads, the data width of the input/output circuit is preferably programmed accordingly. In this way, self-detection and automatic programming are possible without data inputting from the outside.

    Segmented word line architecture
    20.
    发明专利
    Segmented word line architecture 未知

    公开(公告)号：DE19944738A1

    公开(公告)日：2001-03-29

    申请号：DE19944738

    申请日：1999-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

    IPC: G11C11/407 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C7/00

    Abstract: The master word line (WL0)is assigned an additional master word line (MWL1), to form master word line pairs in a memory cell field. The additional master word line can be decoded into several sub-word lines, as can the master word line. One master word line is connected via its sub-word lines (SWL) with memory banks of one logic state and the other master word line is connected via its sub-word lines with memory bands of the other logic state. Hence in word line direction, the memory banks of each logic state can be alternately accommodated. Between the master word lines and the sub word line a single address unit (5) is switched. Both master word lines have several sections of the sub word line assigned to them.

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