公开(公告)号：DE10141841C1

公开(公告)日：2003-03-06

申请号：DE10141841

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  GRUNING VON SCHWERIN ULRIKE ,  RADECKER JOERG

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

公开(公告)号：DE10210434B4

公开(公告)日：2007-12-27

申请号：DE10210434

申请日：2002-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8242

Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

公开(公告)号：DE102004061054A1

公开(公告)日：2006-07-06

申请号：DE102004061054

申请日：2004-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCH JENS ,  STAECKER JENS ,  HOMMEN HEIKO ,  SCHUMACHER KARL ,  SCHIWON ROBERTO ,  SCHMIDT-LANZ MARTIN ,  EFFERENN DIRK

IPC: H01L21/68 ,  G03F7/00

Abstract: The method involves laying of first side of substrate on substrate holder (10), setting of first fluid pressure at the first sub range (26,28,30) of first side of substrate and setting of second fluid pressure at the second sub range of the first side of the substrate. The setting of first fluid pressure and second fluid pressure are implemented after one another. An independent claim is also included for the substrate holding device.

公开(公告)号：DE10209334A1

公开(公告)日：2003-10-09

申请号：DE10209334

申请日：2002-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/76

Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

公开(公告)号：DE10139430A1

公开(公告)日：2003-03-06

申请号：DE10139430

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  GRUENING ULRIKE

IPC: H01L21/762 ,  H01L21/8242

Abstract: Production of isolation trenches between active regions during the manufacture of integrated circuits, especially DRAMs, comprises etching trenches filled with an oxide in a semiconductor substrate (10) to isolate the active regions and form deep trenches (12) filled with polysilicon (14); forming a silicon nitride layer (18) on the surface of the substrate; covering the whole surface of the substrate and the polysilicon with a hard mask layer (20); and forming lateral isolation trenches next to the active regions. Preferred Features: The surface of the polysilicon in the trenches lies than the surface of the silicon nitride layer. The silicon nitride layer is removed by etching on bars between the trenches for a pair of storage capacitors.

公开(公告)号：DE10139432A1

公开(公告)日：2002-10-31

申请号：DE10139432

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/8242 ,  H01L21/82

Abstract: The method involves dividing the structure into substructures that are geometrically simple. The substructures are then processed in separate technological steps. In a first step, a first pattern is formed that is substantially structured in one of two orthogonal directions (x,y), while in a second step, a second pattern is formed that is substantially structured in the other direction.