公开(公告)号：DE10005619A1

公开(公告)日：2001-08-30

申请号：DE10005619

申请日：2000-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  ESTERL ROBERT ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

公开(公告)号：DE10031947A1

公开(公告)日：2002-01-24

申请号：DE10031947

申请日：2000-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  MANYOKI ZOLTAN

IPC: G11C11/22 ,  G11C29/12 ,  G11C29/00 ,  H01L23/58 ,  H01L27/105

Abstract: The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

公开(公告)号：DE10014385A1

公开(公告)日：2001-10-04

申请号：DE10014385

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANYOKI ZOLTAN ,  ESTERL ROBERT ,  BOEHM THOMAS ,  LAMMERS STEFAN

IPC: G05F3/24 ,  H01L23/58 ,  H01L27/085 ,  H03H11/00

Abstract: The voltage divider includes a first chain (A) comprising series-connected, n-type MOS transistors (N0-N4), of similar dimensions and similar gate-source voltages and which operate in the linear region. The voltage to be divided is applied to the ends of the chain, and the divided voltages are available at the respective source terminals. A second chain (B) of MOS transistors (P0-P4), complementary to the first transistors has the same dimensions and number as the first chain. The transistors of the first chain are connected to the transistors of the second chain. Each transistor chain (A,B) produces the gate-source bias voltage for the other transistors chain (B,A).

公开(公告)号：DE10014387C1

公开(公告)日：2001-09-27

申请号：DE10014387

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  MANYOKI ZOLTAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C11/22 ,  G11C7/00

Abstract: A main reference bit line is connected to a reference voltage via a charge switching element such as a p-channel transistor. At least one further reference bit line is connected to the main reference bit line via a compensation switching element for equalising the charge between the reference bit lines. The reference voltage is provided from a reference voltage source. The main reference bit line is connected to three further reference bit lines via three compensation switching elements for charge equalisation. The compensation switching elements may be connected in series. A method of generating a reference voltage on reference bit lines is also claimed.