公开(公告)号：DE10232962B4

公开(公告)日：2004-07-08

申请号：DE10232962

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C11/4097 ,  G11C8/14 ,  G11C8/12 ,  G11C7/10

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

公开(公告)号：DE10224255B4

公开(公告)日：2004-05-06

申请号：DE10224255

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C29/26 ,  G11C29/00

Abstract: A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.

公开(公告)号：DE10201179B4

公开(公告)日：2004-02-19

申请号：DE10201179

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C11/407

Abstract: The circuit has at least two pairs of adjacent banks, a bundle of input/output lines, a controller and a changeover device. Only two bundles of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks. The circuit has at least two pairs of adjacent banks (BK00-BK11), each with a number of memory cells in each bank, a bundle of input/output lines, a controller (120) and a changeover device (30) controllable depending on a clock signal for connecting the input/outputs lines to the first and second halves of the addressed memory bank during first and second half periods. Only two bundles (LDa,b) of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks.

公开(公告)号：DE10224255A1

公开(公告)日：2003-12-24

申请号：DE10224255

申请日：2002-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C29/26 ,  G11C29/00

Abstract: A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.

公开(公告)号：DE10219652A1

公开(公告)日：2003-11-20

申请号：DE10219652

申请日：2002-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

IPC: G11C7/22 ,  G11C11/407 ,  G11C7/20

Abstract: The first clock reception circuit (12) receives first external clock signal and generates first internal clock signal for use in the memory circuit. There is a second clock reception circuit (14) with the same characteristics as the first clock reception circuit. The second clock reception cirucit has lower current consumption than the first circuit. There is a switch block (16), operating according to both internal clock signals and switching-off the first clock reception circuit, if the power-down-precharge-mode is used. The switch block operates according to second internal clock signal, when the first circuit is off. Independent claim is included for operational method of invented memory circuit.

公开(公告)号：DE10146177A1

公开(公告)日：2003-04-10

申请号：DE10146177

申请日：2001-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MORGAN ALAN ,  FISCHER HELMUT

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/48 ,  H01L23/58 ,  H01L21/66 ,  H01L27/04

Abstract: The method involves integrating at least one additional circuit part (3) in the intermediate spaces (4) or cuts between integrated circuits (1) for separation after testing with an external test system (7). The additional circuit part has at least one connecting line (6) directly connected to an associated integrated circuit for controlling a function of the integrated circuit. AN Independent claim is also included for the following: an integrated circuit for implementing the inventive method.

公开(公告)号：DE10137697A1

公开(公告)日：2003-02-27

申请号：DE10137697

申请日：2001-08-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MORGAN ALAN ,  FISCHER HELMUT

IPC: G01R31/3193 ,  G01R31/3177 ,  G01R31/3187 ,  H01L21/66

Abstract: The structures under test are selected in pairs that should have the same properties. Test input terminals are connected to the structures to apply the same test signal. Test output terminals (A1,A2) are connected to an evaluation circuit which compares the test signal responses of the two structures and delivers a comparison result signal. The evaluation circuit may be integrated on the same substrate as the circuit of interest. The two structures may lie in locations of different environmental influence.

公开(公告)号：DE10109486A1

公开(公告)日：2002-09-12

申请号：DE10109486

申请日：2001-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT ,  CHRYSOTOMIDES ATHANASIA

IPC: G11C11/4097 ,  H01L27/108 ,  G11C7/06 ,  G11C7/18

Abstract: The invention relates to an integrated DRAM memory chip comprising sense amplifiers, each configured for the integrated module from a large number of transistor structures and signal conduction pathway structures that are arranged in a regular pattern in cell fields. Said structures comprise amplifier transistors for amplifying the bit line signal, which are structurally identical and lie opposite one another in pairs in neighbouring transistor rows, and signal conduction pathways that are assigned to the transistor rows, running parallel with the latter, for supplying control signals. According to the invention, the signal conduction pathways for the control signals have the same configuration symmetry as the amplifier transistors, in such a way that the amplifier transistors of neighbouring transistor rows have the same proximity to the signal conduction pathway.

公开(公告)号：DE10058398A1

公开(公告)日：2002-06-13

申请号：DE10058398

申请日：2000-11-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KLEHN BERND ,  KRAUSE GUNNAR

IPC: G11C11/408 ,  G11C11/4063

Abstract: An integrated semiconductor memory, includes memory banks (1-4) with memory cells (101-103), at least one word line (104; 106,107). By activating the connected to one of the ends of the word lines (104,106,107) and a switch (120;121, 122) is joined on one side to the other end of the work line and on the other side, to the supply voltage potential (VSS) terminal. A control device (12) can be switched by the switch for deactivating the word line.

公开(公告)号：DE10056881A1

公开(公告)日：2002-05-29

申请号：DE10056881

申请日：2000-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KAISER ROBERT

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/00

Abstract: The memory has a cell field with row lines for selecting memory cells and column lines for reading or writing data signals to/from cells, a row decoder, address lines connected to the row decoder, a control line connected to the row decoder and a delay circuit for connection to the control line to output a signal delayed with respect to a cell selection signal with a current source and a capacitance for charging/discharging by the current source. The memory has a memory cell field with row lines for selecting memory cells and column lines for reading or writing data signals to/from cells, a row decoder for activating row lines, address lines connected to the row decoder for transferring address signals, a control line for indicating the validity of the address signal connected to the row decoder and a delay circuit (8) for connection to the control line to output an output signal delayed with respect to a cell selection signal with a current source and a capacitance for charging or discharging by the current source.