公开(公告)号：DE102004047330A1

公开(公告)日：2006-04-06

申请号：DE102004047330

申请日：2004-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL BERNHARD ,  GERSTMEIER GUENTER

IPC: G11C29/24

Abstract: An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.

公开(公告)号：DE102004023462A1

公开(公告)日：2005-12-15

申请号：DE102004023462

申请日：2004-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL BERNHARD ,  HUBER ANDREAS ,  GERSTMEIER GUENTER

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/525

Abstract: A metallization surface ( 5 ), which acts as an etching stop layer during the production of openings ( 4 ) in a passivation layer ( 3 ) applied to its upper face and protects an interconnect structure ( 6 ) arranged underneath it, is arranged in an uppermost metallization level ( 1 ). A further opening is produced in the metal surface ( 5 ), through which a focused ion beam is aimed at the interconnect structure ( 6 ) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

公开(公告)号：DE10335096A1

公开(公告)日：2004-02-12

申请号：DE10335096

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEGDE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL

IPC: H01L21/318 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/148 ,  H01L29/76

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

公开(公告)号：DE10312195A1

公开(公告)日：2003-10-16

申请号：DE10312195

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ANTONISCHKI GEORG ,  GERSTMEIER GUENTER ,  SANDERS SHANE ,  ZIEGELMAIER MARCO

IPC: G01R31/317 ,  G01R31/3187 ,  G06F7/38

Abstract: An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.

公开(公告)号：DE10043350C2

公开(公告)日：2003-01-02

申请号：DE10043350

申请日：2000-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERSTMEIER GUENTER ,  RICHTER FRANK ,  ROSSKOPF VALENTIN

IPC: G11C29/00 ,  H01L23/544 ,  H01L21/66

公开(公告)号：DE10044537A1

公开(公告)日：2002-03-14

申请号：DE10044537

申请日：2000-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERSTMEIER GUENTER ,  MUTSCHALL DORIS ,  RICHTER FRANK ,  ROSSKOPF VALENTIN ,  SEITZ HELMUT

IPC: G11C29/02 ,  G11C29/50 ,  H01L21/8242 ,  H01L27/105 ,  H01L21/66 ,  G11C29/00 ,  H01L27/115

Abstract: The method involves contacting adjacent memory cells (2) via separate, spaced-apart conductive tracks (1), and then measuring the conductivity between the tracks. A pair of memory cells may be contacted to a predetermined number of parallel, spaced-apart conductive tracks. An Independent claim is included for a circuit device.