Abstract:
PROBLEM TO BE SOLVED: To perform efficient power source control while preventing a malfunction in a memory device provided with a low power consumption mode. SOLUTION: The memory device includes a power source system having many power source devices for supplying voltage or current to the memory device, a controller for supplying, into the power source system, a state control signal to instruct the power source devices to be in an active state or a standby state, and a self-refresh oscillator for generating a self-refresh clock signal with a suitable cycle for refreshing memory cells of the memory device. The controller uses the self-refresh clock signal, and delays transition of the state control signal from the active state to the standby state, relatively to the state change corresponding to at least one external signal receiving from the memory device. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To make it possible to omit a discharge device for limiting a VBB potential by reducing the size and/or the number of VBB pumps. SOLUTION: The memory includes a starting circuit configured so that a second voltage is reduced through parasitic coupling capacitance by boosting a first voltage up to a first value in the state in which the second voltage is grounded and by reducing the first voltage from the first value to a second value in the state in which the second voltage is made floating, and the second voltage is supplied so as to be reduced to a third value in the state in which the first voltage is lower than the second value. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a reference circuit for generating a voltage depending on temperatures, which is used for a mobile information device. SOLUTION: The reference circuit 100 for generating the voltage depending on the temperatures, comprising: a differential amplifier 104; a capacitor 108; a first transistor 106, a first resistor element 110, and a first diode 112, which configure a first circuit; a second resistor element 114 configuring a second circuit; and a second transistor 116 and a third resistor element 118, which configure a third circuit. An input unit 120, which receives a minus voltage of the differential amplifier 104, receives an input voltage VIN, and an output unit 122 connects to one side of the condenser 108, a gate for the first transistor 106, and a gate for the second transistor 116; the first circuit generates a current ITD depending on the temperatures and the second circuit generates a first current ICC. The third circuit is configured for the first current ICC for the second circuit and the current ITD depending on the temperatures such that the third circuit may generate a voltage VREF depending on the temperatures. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
The method involves contacting adjacent memory cells (2) via separate, spaced-apart conductive tracks (1), and then measuring the conductivity between the tracks. A pair of memory cells may be contacted to a predetermined number of parallel, spaced-apart conductive tracks. An Independent claim is included for a circuit device.
Abstract:
A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply voltage and a reference voltage. The voltage source is configured to provide an output voltage out of the boosted supply voltage and based on the reference voltage.
Abstract:
A voltage supply circuit for an integrated circuit comprises a source (1) to apply an internal voltage (Vint) to a supply lead (3), a connected regulation circuit (4) comprising and ON/OFF control that prevents the voltage deviating from a limiting value on the basis of a capacitive charge store (5). Independent claims are also included for the following: (A) an integrated DRAM memory circuit as above;and (B) a control process for the above.