公开(公告)号：DE10244569A1

公开(公告)日：2003-04-24

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

Abstract: A semiconductor gate is capped with a pad oxide layer (20), which is bounded by one or more isolation trenches filled with silicon oxide. The pad oxide layer is thickened to a specified thickness to form a sacrificial oxide layer, then the sacrificial oxide layer is stripped and the semiconductor gate is capped with gate oxide layer. An Independent claim is also included for semiconductor structure.

公开(公告)号：DE10350354A1

公开(公告)日：2004-05-27

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78 ,  H01L21/336

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

公开(公告)号：DE10341576A1

公开(公告)日：2004-03-18

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/20 ,  H01L21/8242

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

公开(公告)号：DE10244569B4

公开(公告)日：2006-08-10

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10305729A1

公开(公告)日：2003-08-28

申请号：DE10305729

申请日：2003-02-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHAKRAVARTI ASHIMA B ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/00 ,  H01L21/316 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/324

Abstract: An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.