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    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS
    1.
    发明申请
    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS 审中-公开
    用于均匀氧化物厚度的双栅氧化工艺

    公开(公告)号：WO0237561A2

    公开(公告)日：2002-05-10

    申请号：PCT/US0143859

    申请日：2001-11-06

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    Semiconductor device subject to stress deformation and manufacturing method thereof
    2.
    发明专利
    Semiconductor device subject to stress deformation and manufacturing method thereof 有权
    受应力变形的半导体器件及其制造方法

    公开(公告)号：JP2007110098A

    公开(公告)日：2007-04-26

    申请号：JP2006247813

    申请日：2006-09-13

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： SCHENK ANDRE ,  TEWS HELMUT

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method of which a stress is adjusted for improved performance.
    SOLUTION: A gate electrode 104 is electrically insulated from a semiconductor substrate (bulk silicon substrate, SOI layer, or the like) 102. A first side wall spacer 110 is formed along the side wall of the gate electrode 104. A sacrifice side wall spacer is so formed as to adjoin the first side wall spacer 110. The sacrifice side wall spacer and the first side wall spacer 110 cover the semiconductor substrate 102. A flattened layer is formed to cover the semiconductor substrate 102 so that a part of the flattened layer adjoins the sacrifice side wall spacer. The sacrifice side wall spacer is removed, and a recess is formed in the semiconductor substrate 102 by etching. The recess is substantially arranged between the first side wall spacer 110 and a part of the flattened layer. A semiconductor material (SiGe, SiC, or the like) 116 is deposited in the recess.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 解决的问题：提供调整应力以提高性能的半导体器件及其制造方法。 解决方案：栅电极104与半导体衬底（体硅衬底，SOI层等）102电绝缘。沿着栅电极104的侧壁形成第一侧壁间隔物110.牺牲 侧壁间隔件形成为邻接第一侧壁间隔物110.牺牲侧壁隔离物和第一侧壁隔离物110覆盖半导体衬底102.形成平坦层以覆盖半导体衬底102，使得部分 扁平层与牺牲侧壁间隔物邻接。 除去牺牲侧壁间隔物，通过蚀刻在半导体衬底102中形成凹部。 凹部基本上布置在第一侧壁间隔件110和平坦层的一部分之间。 在凹部中沉积半导体材料（SiGe，SiC等）116。 版权所有（C）2007，JPO＆INPIT

    3.
    发明专利
    未知

    公开(公告)号：DE10244569B4

    公开(公告)日：2006-08-10

    申请号：DE10244569

    申请日：2002-09-25

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

    IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

    Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

    6.
    发明专利
    未知

    公开(公告)号：DE10350354B4

    公开(公告)日：2007-08-16

    申请号：DE10350354

    申请日：2003-10-29

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

    IPC: H01L21/316 ,  H01L21/314 ,  H01L21/318 ,  H01L21/321 ,  H01L21/336 ,  H01L29/04 ,  H01L29/78

    Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

    8.
    发明专利
    未知

    公开(公告)号：DE10344862A1

    公开(公告)日：2004-04-15

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    9.
    发明专利
    未知

    公开(公告)号：DE10246306A1

    公开(公告)日：2003-04-30

    申请号：DE10246306

    申请日：2002-10-04

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

    Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

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