公开(公告)号：DE102004052611A1

公开(公告)日：2006-05-04

申请号：DE102004052611

申请日：2004-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS ,  KUND MICHAEL ,  MUELLER GERHARD

IPC: H01L27/24 ,  H01L21/283

Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

公开(公告)号：DE102004042171A1

公开(公告)日：2006-04-20

申请号：DE102004042171

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: G11C7/24

Abstract: The arrangement has a set of memory cells (101) whose memory status can be modified by applying voltage at two poles of the memory cells. The two poles of the memory cells are short-circuited through a switching arrangement (130), where the memory cells are selectively manufactured. The memory cells are arranged like an array, and each of the two poles of the memory cells are provided with respective bit line and word line. An independent claim is also included for a method for protecting a memory arrangement.

公开(公告)号：DE102004037152A1

公开(公告)日：2006-03-23

申请号：DE102004037152

申请日：2004-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: G11C16/02

Abstract: Memory cell (100) based on phase change memory mechanism contains memory element (10) with phase change material (16') as memory medium (16) and selection element (20) with threshold value characteristic. Memory and selection elements are series connected, with selection element typically of resistive type.Preferably selection element comprises or provides high-ohmic connection to memory element at applied potential difference below preset first threshold voltage, but low-ohmic connection at above second preset threshold voltage. Independent claims are included for memory module and for its operation.

公开(公告)号：DE102005001668A1

公开(公告)日：2006-03-16

申请号：DE102005001668

申请日：2005-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HAPP THOMAS

IPC: G11C16/00 ,  G11C11/4099

Abstract: The circuit has a phase-changeable memory cell (1) with phase changeable material. An evaluating processor unit has a comparator that compares an electrical value that is dependant on a resistance value of the material with a reference value and determines the condition of the cell based on the comparison result. A reference value unit is designed to generate the reference value dependent on temperature of the material.

公开(公告)号：DE102004019860B4

公开(公告)日：2006-03-02

申请号：DE102004019860

申请日：2004-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  KUND MICHAEL

IPC: G11C13/02 ,  G11C16/02

公开(公告)号：DE102005014508A1

公开(公告)日：2005-10-20

申请号：DE102005014508

申请日：2005-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  ROEHR THOMAS

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G9/22 ,  H01L23/525 ,  H01L27/24

公开(公告)号：DE102004007633A1

公开(公告)日：2005-09-08

申请号：DE102004007633

申请日：2004-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  PINNOW CAY-UWE ,  KUND MICHAEL

IPC: G11C11/15 ,  G11C11/22 ,  G11C13/00 ,  G11C13/02 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

Abstract: The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.

公开(公告)号：DE10356285A1

公开(公告)日：2005-06-30

申请号：DE10356285

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： UFERT KLAUS-DIETER ,  SYMANCZYK RALF ,  HAPP THOMAS ,  PINNOW CAY-UWE

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

公开(公告)号：DE10345475A1

公开(公告)日：2005-05-04

申请号：DE10345475

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

公开(公告)号：DE102008030858A1

公开(公告)日：2009-02-05

申请号：DE102008030858

申请日：2008-06-30

Applicant: INFINEON TECHNOLOGIES AG ,  QIMONDA AG

Inventor： PHILIPP JAN BORIS ,  HAPP THOMAS ,  NIRSCHL THOMAS

IPC: G11C29/24 ,  G11C13/02

Abstract: One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.