公开(公告)号：WO2006005321A3

公开(公告)日：2006-02-23

申请号：PCT/DE2005001209

申请日：2005-07-08

Applicant: INFINEON TECHNOLOGIES AG ,  ILICALI GUERKAN ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

Inventor： ILICALI GUERKAN ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/78648

Abstract: The invention relates to a substrate comprising a buried layer. According to the invention, a silicon carrier wafer has a buried first silicon-germanium-carbon layer, on which a silicon layer is configured.

Abstract translation: 具有掩埋层的衬底在硅载体晶片上具有其上形成有硅层的掩埋的第一硅 - 锗 - 碳层。

公开(公告)号：WO2004038802A3

公开(公告)日：2004-09-10

申请号：PCT/DE0303354

申请日：2003-10-10

Applicant: INFINEON TECHNOLOGIES AG ,  BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

Abstract: Disclosed is an integrated circuit arrangement (140), among others, comprising a preferably planar transistor (142) and a capacitor (144). The lower electrode of the capacitor (144) is disposed within an SOl substrate along with a channel section of the transistor (142). The inventive circuit arrangement (140) is easy to produce and has excellent electronic properties.

Abstract translation: 尤其公开了包含优选平面晶体管（142）和电容器（144）的集成电路装置（140）。 电容器（144）的下电极与SOI衬底中的晶体管（142）的沟道区共同布置。 电路装置（140）容易制造并具有优异的电子特性。

公开(公告)号：WO03088310A2

公开(公告)日：2003-10-23

申请号：PCT/DE0301281

申请日：2003-04-16

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  STAEDELE MARTIN

Inventor： HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  STAEDELE MARTIN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L

CPC classification number: H01L21/76262 ,  H01L21/76251

Abstract: The invention relates to a substrate (600) which is provided with a support layer (501). An insulator layer (502) is applied to the support layer (501), comprising at least two areas having respectively different thicknesses. A semi-conductor layer (303) having an FD-area (304) and a PD-area (305) is applied to the surface of the insulating layer (502), comprising a planar surface. The planar surface is the surface which is opposite the insulating layer (502).

Abstract translation: 本发明提供一种基板（600），其包括载体层（501）。 其中的绝缘层（502）被施加，包括各自具有不同厚度的至少两个区域的载体层（501）上。 在绝缘体层的表面（502）是与FD区域（304）和PD区域（305）的半导体层（303）被施加，其具有平坦表面，所述平坦表面与所述表面的绝缘体层（502） 对面。

公开(公告)号：WO0106542A3

公开(公告)日：2001-07-19

申请号：PCT/DE0002316

申请日：2000-07-17

Applicant: INFINEON TECHNOLOGIES AG ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

Abstract translation: 在衬底（1）上构建双栅MOSFET半导体层结构。 这在半导体沟道层区的相对的端面由第一和在其之间的半导体沟道层区域（4A）被嵌入第二栅电极（10A，10B），以及源极（2A）和漏极区域（2b）中的 （4A）被布置。 在其中一个栅电极（10B）上提供至少一个另外的半导体沟道层区域（6A），其端面同样与源极（2A）和漏极区域（2B）接触。

公开(公告)号：WO0137342A2

公开(公告)日：2001-05-25

申请号：PCT/DE0003982

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L25/00

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

Abstract translation: 该晶体管的第一源极/漏极区（S / D1），其上的沟道区相邻的（KA），一个与其相邻的第二源极/漏极区（S / D2），栅极电介质和栅极电极。 所述电容器的第一电容器电极（SP）被连接到所述第一源极/漏极区（S / D1）。 绝缘结构完全围绕的电路的绝缘区域。 在至少所述第一电容器电极（SP）和所述第一源极的绝缘区/漏极区（S / D1）被布置，而第二源极/漏极区（S / D2）和所述电容器的第二电容器电极上的绝缘外 排列区域。 因为绝缘结构的电荷不会丢失由于从充电和放电电容器之间的第一电容器电极（SP）的漏电流。 在沟道区中的隧穿势垒（T），其设置（KA），是在绝缘结构的部分。 电容器电介质（KD），（SP）分离所述第二电容器电极的第一电容器电极，在绝缘结构的部分。

公开(公告)号：WO2004038770A3

公开(公告)日：2004-09-23

申请号：PCT/DE0303355

申请日：2003-10-10

Applicant: INFINEON TECHNOLOGIES AG ,  BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

Abstract: Disclosed is an integrated circuit arrangement (120), among others, comprising a transistor (122), preferably a FinFET, and a capacitor (124). The lower electrode of the capacitor (124) is disposed within an SOl substrate along with a channel section of the transistor (122). The inventive circuit arrangement (120) is easy to produce and has excellent electronic properties.

Abstract translation: 进行了说明，除其他外，集成电路装置（120）包括一个晶体管（122），优选地为所谓的FinFET，和电容器（124）。 电容器（124）的下部电极与在SOI衬底的晶体管（122）的沟道区布置在一起。 所述的电路装置（120）是容易制造并具有优良的电子特性。

公开(公告)号：WO2004040668A3

公开(公告)日：2004-07-08

申请号：PCT/DE0303612

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.

Abstract translation: 本发明涉及一种场效应晶体管装置和一种电路阵列。 场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。 此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。 纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

公开(公告)号：WO2004023519A2

公开(公告)日：2004-03-18

申请号：PCT/EP0309297

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01R11/22 ,  H01R13/62 ,  H01L

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

Abstract: The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), said rib (FIN) having a substantially rectangular shape, according to a cross-sectional view extending in a perpendicular manner with respect to the longitudinal direction of the rib (FIN), comprising an upper rib side (10) and opposite lateral rib surfaces (12, 14); a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1) which is distanced by means of a second insulating layer (22) from said one lateral rib surface (12) and distanced by means of a third insulating layer (29) from the memory layer (18), said gate electrode (WL1) being electrically insulated in relation to the channel region and being embodied in order to control the electrical conductivity thereof.

Abstract translation: 本发明涉及一种具有多个存储器单元，每个存储器单元包括一个半导体存储器：第一导电掺杂接触区（S / D），第二导电掺杂接触区（S / D）和一个介于沟道区，其中（在网状肋FIN ）形成的半导体材料，以及（在肋FIN的纵向方向上按此次序）被布置成一个在另一个后面，其中所述鳍（FIN）至少在垂直（在沟道区延伸到所述肋FIN的长度方向）截面，具有一肋顶部的大致rechtsecksförmige形状 （10）和相对的肋的侧表面（12，14）; 所设计的用于通过第一绝缘体层编程所述存储器单元存储层（18）（20）间隔开的肋顶部（10）布置，其中，在一个正常的方向经由肋的侧表面中的至少一个（12）（12）的存储层（18） 肋侧表面（12）突出，以使所述一个肋侧表面（12）和肋顶部（10）形成用于从沟道区的载流子到所述存储层注入（18）的喷射边缘（16）; 和至少一个栅极电极（WL1），其通过第二绝缘体层隔开一个（22）的肋侧表面（12）和通过所述存储层（18）的第三绝缘层（29），其中所述沟道区相对的栅电极（WL1），其电 是绝缘的，并适于控制其导电性。

公开(公告)号：WO0243109A2

公开(公告)日：2002-05-30

申请号：PCT/DE0104358

申请日：2001-11-21

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78654

Abstract: The invention relates to a planar field effect transistor comprising a barrier layer that lies adjacent to and/or below part of the gate region. Said barrier layer is configured between the source region and the channel region and/or between the drain region and the channel region in such a way that there is practically no diffusion of the doping atoms from the source region and the drain region into the channel region, but that electric charge carriers can tunnel through the barrier layer.

Abstract translation: 一种平面场效应晶体管具有邻近所述栅极区和/或之下的栅极区域的一部分的阻挡层，其中所述源极区和沟道区之间的势垒层/或漏极区和沟道区之间的被配置为使得 基本上没有掺杂剂原子的扩散是存在于源区和漏区可在沟道区中进行，但电荷载流子隧穿可以通过将阻挡层。

公开(公告)号：DE50310011D1

公开(公告)日：2008-07-31

申请号：DE50310011

申请日：2003-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LEHMANN VOLKER ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/334 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94

Abstract: Semiconductor substrate comprises a carrier substrate (1), a semiconductor component layer (3), an insulating layer (2) arranged between the carrier substrate and the semiconductor component layer, recesses (P) formed in a surface facing the insulating layer in the carrier substrate, a dielectric layer (D) formed on the surface of the recesses and carrier substrate, and an electrically conducting layer (E2) formed in the recesses to produce capacitor electrodes. A further electrically conducting layer is formed in the carrier substrate to form capacitor counter electrodes in the region of the recesses. An Independent claim is also included for a process for the production of a semiconductor substrate.