公开(公告)号：DE102005015002A1

公开(公告)日：2006-10-05

申请号：DE102005015002

申请日：2005-04-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFSAES MARKUS ,  SCHNABEL FLORIAN ,  RUF BERNHARD

IPC: G11C29/24 ,  G11C8/02 ,  G11C29/18

Abstract: The method involves assigning an identifier to each fuse of an integrated memory circuit based on a provided net list, and assigning address information to a group of fuses. Position data of the fuses are determined from a layout, generated based on the net list, to determine if the position data are in conjunction with the net list based on the fuse identifiers. Repair position data are produced from the obtained position data of the fuses and repair data from a tester mechanism. The fuses are then programmed using the repair position data to repair the integrated memory circuit. The net list describes the interconnected electronic components and fuses included in the integrated memory circuit. The address information indicates to which redundant storage areas the fuses are designated or assigned. Allocation between the address information and position data of the fuses is determined based on the conjunction relationship of the position data and address information with respect to the net list. The repair position indicates the position of the fuse that can be programmed for repair.

公开(公告)号：DE102004055674A1

公开(公告)日：2006-05-24

申请号：DE102004055674

申请日：2004-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  POLNEY JENS

IPC: G11C7/14

Abstract: A device for writing/reading a memory cell (1) has first (5) and second (6) devices for influencing a selecting transistor's (2) threshold voltage against the effects from a surrounding temperature. The first device is an electric voltage generator (5) for attaching voltage to the selecting transistor's substrate trough (4). An independent claim is also included for a method for writing/reading a memory cell in a semiconductor device.

公开(公告)号：DE10338022A1

公开(公告)日：2005-03-31

申请号：DE10338022

申请日：2003-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  POLNEY JENS

IPC: G11C8/00 ,  G11C8/10 ,  G11C29/00

Abstract: In order to reset a deactivating signal at a low status earlier than would have occurred through a corresponding evaluation of an address attached to an address bus, a control signal (S) attaches to a decoding circuit, which can ensue via an address line (AL) (11). The control signal is made available by a corresponding control circuit (12) via the AL of a second decoding circuit (5). Independent claims are also included for the following: (a) An address-decoding circuit for decoding an address; (b) and for an integrated circuit with an address-decoding circuit.

公开(公告)号：DE10048477A1

公开(公告)日：2002-04-25

申请号：DE10048477

申请日：2000-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  BEITEL GERHARD ,  MAINKA GERD ,  SCHNABEL FLORIAN

IPC: C09G1/02 ,  C23F3/00 ,  H01L21/321