公开(公告)号：DE10354112A1

公开(公告)日：2005-06-30

申请号：DE10354112

申请日：2003-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KALLSCHEUER JOCHEN ,  SCHNEIDER HELMUT WALTER ,  RUF BERNHARD ,  SALCHNER REINHARD

IPC: G06F11/20 ,  G11C29/00 ,  H01L21/31 ,  H01L21/66 ,  H01L21/768 ,  H01L21/822 ,  H01L23/525

Abstract: A photosensitive resist is applied onto wafers (6) identified for repair. A mask (1) is built corresponding to fuse coordinates that are specific to a relevant chip and correspond to the repair. Wafers treated with the photosensitive resist are exposed to light through the mask with an exposure device (2). The fuse coordinates are entered in a control unit (9). An independent claim is also included for a system for a method for repairing memory chips.

公开(公告)号：DE10039350A1

公开(公告)日：2002-02-28

申请号：DE10039350

申请日：2000-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  GRUBER ARNDT ,  RUF BERNHARD

IPC: G01R31/3177 ,  G11C7/00 ,  G11C29/00 ,  H01L21/66 ,  H01L31/0328

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

公开(公告)号：DE10039350C2

公开(公告)日：2003-04-03

申请号：DE10039350

申请日：2000-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  GRUBER ARNDT ,  RUF BERNHARD

IPC: G01R31/3177 ,  G11C7/00 ,  G11C29/00 ,  H01L21/66 ,  H01L31/0328

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

公开(公告)号：DE102005015002A1

公开(公告)日：2006-10-05

申请号：DE102005015002

申请日：2005-04-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFSAES MARKUS ,  SCHNABEL FLORIAN ,  RUF BERNHARD

IPC: G11C29/24 ,  G11C8/02 ,  G11C29/18

Abstract: The method involves assigning an identifier to each fuse of an integrated memory circuit based on a provided net list, and assigning address information to a group of fuses. Position data of the fuses are determined from a layout, generated based on the net list, to determine if the position data are in conjunction with the net list based on the fuse identifiers. Repair position data are produced from the obtained position data of the fuses and repair data from a tester mechanism. The fuses are then programmed using the repair position data to repair the integrated memory circuit. The net list describes the interconnected electronic components and fuses included in the integrated memory circuit. The address information indicates to which redundant storage areas the fuses are designated or assigned. Allocation between the address information and position data of the fuses is determined based on the conjunction relationship of the position data and address information with respect to the net list. The repair position indicates the position of the fuse that can be programmed for repair.