公开(公告)号：EP2140458A4

公开(公告)日：2010-05-05

申请号：EP07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L C ,  RADENS CARL ,  WONG KEITH K H ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

CPC classification number: G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

公开(公告)号：WO03005447A8

公开(公告)日：2004-02-19

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：WO03005447A2

公开(公告)日：2003-01-16

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。 该工艺消除了对M0金属化层的需求。

公开(公告)号：WO2007023011B1

公开(公告)日：2007-07-12

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：JP2000323578A

公开(公告)日：2000-11-24

申请号：JP37247499

申请日：1999-12-28

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01H85/046

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit which has a improved fuse structure and a laser fuse link. SOLUTION: A fuse structure within an integrated circuit chi is described which includes an insulated semiconductor substrate, a fuse band 4 consisting of a plurality of parallel fuse links 402, 404, and 406 on the same plane and united with the insulated semiconductor substrate, and voids 410 and 412 scattered among fuse links each in a pair and extending beyond the plane demarcated by the fuse links on the same plane. The voids 410 and 412, surrounding the spot 420 which should be hit with a laser beam during the operation of fuse fusion function as crack stopper for preventing damages to the adjacent circuit element or other existing fuse link. Closer pitch between fuses can be obtained by forming and positioning the voids properly.

公开(公告)号：JPH11330402A

公开(公告)日：1999-11-30

申请号：JP9246899

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  JAIPRAKASH VENKATACHALAM C ,  BRONNER GARY ,  RADENS CARL ,  BEINTNER JOCHEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion of the height of an embedded strap by making the depression extending below the surface of the substrate in a filling material, to determine the top surface of a buried strap and by making a recess extending below the top surface of the embedded strap in a collar to determine the bottom side surface. SOLUTION: A substrate includes a partially completed trench capacitor. A collar 110 is made on the upper portion of the trench capacitor. A trench 108 is filled with a filling material 112 and the inner sidewall of the collar is lined with the filling material 112. A recess having a predetermined depth is made in the filling material 112. The depth of the recess actually determines the top portion of an embedded strap. A hole is made in the collar to the depth of 120 below the top surface 118 of the filling material 112. A layer 122 is removed from the side of the trench 108 and the top surface of a semiconductor device 100, while a recessed region 124 filled with the material of the layer 122 is left.

公开(公告)号：WO2009120612A2

公开(公告)日：2009-10-01

申请号：PCT/US2009037910

申请日：2009-03-23

Applicant: IBM ,  CHENG KANGGUO ,  RADENS CARL

Inventor： CHENG KANGGUO ,  RADENS CARL

IPC: H01L21/8238 ,  G06F9/45 ,  G06F17/50 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

Abstract translation: 施加有拉伸和/或压缩应变的半导体器件以及制造半导体器件和设计结构以增强沟道应变的方法。 该方法包括形成用于NFET和PFET的栅极结构，并且使用相同的沉积和蚀刻工艺在用于NFET和PFET的栅极结构上形成侧壁。 该方法还包括在NFET和PFET的源极和漏极区中提供应力材料。

公开(公告)号：JP2004006772A

公开(公告)日：2004-01-08

申请号：JP2003093635

申请日：2003-03-31

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit having an improved fuse structure part and laser fuse links. SOLUTION: The fuse structure part in an integrated circuit chip comprises an insulated semiconductor substrate, a fuse bank 410 which is constituted of a plurality of the parallel fuse links 402, 404 and 404 on the same plane and which are integrated with the insulated semiconductor substrate and voids 410 and 412 which scatter between pairs of fuse links and which extend across the plane delimited by the fuse links on the same plane. The voids 410 and 412 surrounding a spot 420 to be hit by a laser beam during a fusing operation function as crack stops for preventing damage against an adjacent circuit element or the other existing fuse link. Thus, a denser pitch between fuses can be obtained by suitably forming and positioning the voids. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000216354A

公开(公告)日：2000-08-04

申请号：JP2000005490

申请日：2000-01-14

Applicant: IBM ,  SIEMENS AG

Inventor： MANDELMAN JACK ,  RADENS CARL ,  GRUENING ULRIKE

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an embedded self-aligned strap in a deep storage trench. SOLUTION: A spacer 42/52 is formed on the wall face of a recess on an already filled deep trench capacitor 30. A plug 46/54 is formed within the region between spacers. A photoresist is stuck onto the spacer 42/54 and the plug 46/54 and a peripheral material 40, and a part of the plug 46/54, the spacer 42/52, and the material 40 is exposed. The spacer part not covered with the photoresist is selectively etched. A board and a trench part exposed by the removal of the spacer are selectively etched. An isolation region 58 is formed within the space made etching.

公开(公告)号：JPH11176930A

公开(公告)日：1999-07-02

申请号：JP26992298

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a layer which is uniform in flatness and thickness on a semiconductor chip or on a semiconductor device provided with a trench. SOLUTION: An oxide thermal pad layer 104 is formed on a semiconductor substrate 102 through a thermal oxidation method, a nitride insulating layer 106, a buffer layer 108 of oxide or preferably TEOS(tetraethyl oxosilane), and a SiN mask layer 110 are formed thereon through a CVD(chemical vapor deposition) method, and a hard mask layer 112 containing BSG(borosilicate glass) or TEOS is formed on the mask layer 110. Then, a semiconductor device is manufactured, a trench is provided to the device, filler is filled, a polishing is carried out up to a pad stop, and an etching operation is carried out using the buffer layer as an etching stopper for removing the pad stop and the buffer layer, whereby a surface layer which is nearly flat and uniform in thickness can be obtained.