公开(公告)号：US20200328309A1

公开(公告)日：2020-10-15

申请号：US16720231

申请日：2019-12-19

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Zhaohao ZHANG ,  Tianchun YE

IPC: H01L29/78 ,  H01L29/66

Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1≤x≤0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

公开(公告)号：US20160087062A1

公开(公告)日：2016-03-24

申请号：US14688523

申请日：2015-04-16

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Yongkui ZHANG ,  Zhiguo ZHAO ,  Zhiyong LU ,  Huilong ZHU

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/4916 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes: a plurality of fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of fin structures, wherein the gate stack structure includes a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of fin structures and beneath the gate stack structure; and source/drain regions on the plurality of fin structures and at both sides of the gate stack structure along the first direction.

Abstract translation: 半导体器件包括：沿着第一方向在衬底上延伸的多个翅片结构; 栅极堆叠结构，其沿着第二方向延伸并且跨越所述多个鳍状结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个翅片结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个鳍结构上的源/漏区，以及沿着第一方向的栅叠层结构的两侧。

公开(公告)号：US20150311200A1

公开(公告)日：2015-10-29

申请号：US14397822

申请日：2013-08-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Xiaolong MA ,  Weijia XU ,  Qiuxia XU ,  Huilong ZHU

IPC: H01L27/088 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract translation: FinFET器件及其制造方法。 FinFET器件包括多个翅片，每个翅片沿基底上的第一方向延伸; 多个栅极堆叠，每个栅极叠堆叠跨越所述多个散热片并沿第二方向延伸; 多个源/漏区对，每个源极/漏极区对的各个源极/漏极区在第二方向上设置在每个栅极堆叠的相对侧上; 以及多个通道区域，每个沟道区域包括在相应的源极/漏极对的各个源极/漏极区域之间的相应鳍片的一部分，其中每个鳍片包括在第二方向的相对侧表面上的多个突起单元。

公开(公告)号：US20250133785A1

公开(公告)日：2025-04-24

申请号：US18907334

申请日：2024-10-04

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qingzhu ZHANG ,  Lianlian LI ,  Anyan DU ,  Huaxiang YIN ,  Lei CAO ,  Jiaxin YAO ,  Zhaohao ZHANG ,  Qingkun LI ,  Guanqiao SANG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure provides a stacked nanosheet gate-all-around device with an air spacer and a manufacturing method. The device includes: a substrate, where a first dielectric layer is on the substrate, a gap array is in the first dielectric layer, the gap array includes multiple gap units, and each gap unit is in a fin shape above the substrate; a nanosheet stacking portion above the gap unit, including a stack formed by multiple nanosheets, and the stack formed by the nanosheets constitutes multiple conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region on two opposite sides of the nanosheet stacking portion, where an empty spacer is between the source/drain region and the gate-all-around. An interior of the gap array and an interior of the empty spacer are filled with at least one of air, a reducing gas, or an inert gas.

公开(公告)号：US20240379794A1

公开(公告)日：2024-11-14

申请号：US18462613

申请日：2023-09-07

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Peng ZHAO ,  Zhenhua WU ,  Jiaxin YAO

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.

公开(公告)号：US20220085070A1

公开(公告)日：2022-03-17

申请号：US17423082

申请日：2019-11-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Zhaozhao HOU ,  Tianchun YE ,  Chaolei LI

IPC: H01L27/11597 ,  H01L21/28 ,  H01L29/51 ,  H01L27/1159

Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.

公开(公告)号：US20210151557A1

公开(公告)日：2021-05-20

申请号：US16824761

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Xiaohong CHENG ,  Qingzhu ZHANG ,  Huaxiang YIN ,  Wenwu WANG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

公开(公告)号：US20160268391A1

公开(公告)日：2016-09-15

申请号：US14812490

申请日：2015-07-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu ZHANG ,  Lichuan ZHAO ,  Xiongkun YANG ,  Huaxiang YIN ,  Jiang YAN ,  Junfeng LI ,  Tao YANG ,  Jinbiao LIU

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/167 ,  H01L29/45 ,  H01L21/265

CPC classification number: H01L29/665 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28097 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66795

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Abstract translation: 一种形成金属硅化物的方法。 该方法包括：提供具有翅片的基板，形成在翅片上的栅极和形成在栅极的相对侧上的间隔件; 沉积Ti金属层; 硅化Ti金属层; 并除去未反应的Ti金属层。 由于Ti原子具有相对稳定的特性，扩散主要发生在Si原子上，而Ti原子在热退火过程中很少扩散。 结果，可以在耗尽区域中防止电流泄漏，从而可以降低衬底的漏电流。