公开(公告)号：US09373622B2

公开(公告)日：2016-06-21

申请号：US14721386

申请日：2015-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Hong Yang ,  Qingzhu Zhang ,  Qiuxia Xu

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.

Abstract translation: CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域 栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层 每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。 根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能 。

公开(公告)号：US11411091B2

公开(公告)日：2022-08-09

申请号：US16954776

申请日：2019-10-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Tianchun Ye ,  Qingzhu Zhang ,  Jiaxin Yao

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786 ,  H01L27/092

Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.

公开(公告)号：US11024708B1

公开(公告)日：2021-06-01

申请号：US16824761

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

公开(公告)号：US09431504B2

公开(公告)日：2016-08-30

申请号：US14696616

申请日：2015-04-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Yongkui Zhang ,  Zhiguo Zhao ,  Zhiyong Lu ,  Huilong Zhu

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/265

CPC classification number: H01L29/4916 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545

Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

Abstract translation: 提供一种半导体器件，其具有沿着第一方向在衬底上延伸的多个鳍结构; 栅极堆叠结构，其沿着第二方向延伸并跨越所述多个Fin结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个鳍结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个Fin结构上的源极/漏极区域以及沿着第一方向的栅极堆叠结构的两侧。 还提供了一种制造半导体器件的方法。

公开(公告)号：US09385212B2

公开(公告)日：2016-07-05

申请号：US14725666

申请日：2015-05-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Guilei Wang ,  Huilong Zhu

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上形成沿第一方向延伸的多个翅片; 在翅片上形成沿着第二方向延伸的虚拟栅极堆叠; 在第一方向上在虚拟栅极堆叠的相对侧上形成栅极间隔物; 在第一方向上在栅极间隔物的相对侧的翅片的顶部外延生长凸起的源极/漏极区域; 通过栅极间隔物作为掩模，通过凸起的源极/漏极区进行轻掺杂离子注入，以在第一方向上在栅极间隔物的相对侧的鳍中形成源极/漏极延伸区域; 去除虚拟栅极堆叠以形成栅极沟槽; 以及在栅极沟槽中形成栅叠层。

公开(公告)号：US20150228480A1

公开(公告)日：2015-08-13

申请号：US14688788

申请日：2015-04-16

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Zuozhen Fu ,  Xiaolong Ma ,  Dapeng Chen

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract translation: 公开了堆叠的纳米线MOS晶体管的制造方法。 一方面，该方法包括在基板上沿着第一方向形成多个散热片。 该方法还包括在每个翅片中形成由多个纳米线构成的纳米线堆叠。 该方法还包括在纳米线堆叠中沿着第二方向形成栅极堆叠，所述栅极堆叠围绕纳米线堆叠。 该方法还包括在栅极堆叠的两侧形成源极/漏极区域，构成沟道区域的各个源极/漏极区域之间的纳米线。 可以通过多次蚀刻形成一叠纳米线，横向蚀刻沟槽并填充沟槽。 横向蚀刻工艺包括具有内部切线和横向蚀刻的各向同性干法蚀刻，以及沿相应晶体学方向选择性蚀刻的湿蚀刻。

公开(公告)号：US11839085B2

公开(公告)日：2023-12-05

申请号：US17423082

申请日：2019-11-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Zhaozhao Hou ,  Tianchun Ye ,  Chaolei Li

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H10B51/30

Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.

公开(公告)号：US11476328B2

公开(公告)日：2022-10-18

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US11069808B2

公开(公告)日：2021-07-20

申请号：US16720231

申请日：2019-12-19

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Qingzhu Zhang ,  Zhaohao Zhang ,  Tianchun Ye

IPC: H01L29/78 ,  H01L29/66

Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1≤x≤0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

公开(公告)号：US20160087063A1

公开(公告)日：2016-03-24

申请号：US14696616

申请日：2015-04-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Yongkui Zhang ,  Zhiguo Zhao ,  Zhiyong Lu ,  Huilong Zhu

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/324

CPC classification number: H01L29/4916 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545

Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

Abstract translation: 提供一种半导体器件，其具有沿着第一方向在衬底上延伸的多个鳍结构; 栅极堆叠结构，其沿着第二方向延伸并跨越所述多个Fin结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个鳍结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个Fin结构上的源极/漏极区域以及沿着第一方向的栅极堆叠结构的两侧。 还提供了一种制造半导体器件的方法。