中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.039 seconds)

    MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIASING METHOD
    11.
    发明公开
    MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIASING METHOD 审中-公开

    公开(公告)号：US20230197152A1

    公开(公告)日：2023-06-22

    申请号：US17996194

    申请日：2020-04-14

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Jianguo YANG ,  Xiaoxin XU ,  Ming LIU

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79

    Abstract: Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.

    WRITING METHOD AND ERASING METHOD OF FUSION MEMORY
    13.
    发明申请
    WRITING METHOD AND ERASING METHOD OF FUSION MEMORY 有权

    公开(公告)号：US20220115052A1

    公开(公告)日：2022-04-14

    申请号：US17426053

    申请日：2019-01-28

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Tiancheng GONG ,  Ming LIU

    IPC: G11C11/22 ,  G11C16/14 ,  G11C16/34

    Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

    SELECTOR BASED ON TRANSITION METAL OXIDE AND PREPARATION METHOD THEREFOR
    14.
    发明申请
    SELECTOR BASED ON TRANSITION METAL OXIDE AND PREPARATION METHOD THEREFOR 审中-公开

    公开(公告)号：US20200058704A1

    公开(公告)日：2020-02-20

    申请号：US16486614

    申请日：2017-02-22

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Shibing LONG ,  Qi LIU ,  Ming LIU

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration. In addition, the selector for the resistive random access memory of the present invention has advantages of a simple structure, easy for integration, a low cost, a good uniformity, and compatibility with a CMOS process.

    METHOD FOR COLLECTING SIGNAL WITH SAMPLING FREQUENCY LOWER THAN NYQUIST FREQUENCY
    15.
    发明申请
    METHOD FOR COLLECTING SIGNAL WITH SAMPLING FREQUENCY LOWER THAN NYQUIST FREQUENCY 有权
    采集频率低于NYQUIS频率的信号采集方法

    公开(公告)号：US20150326246A1

    公开(公告)日：2015-11-12

    申请号：US14805868

    申请日：2015-07-22

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Dongmei LI ,  Xiaojing LI ,  Shengfa LIANG ,  Hao ZHANG ,  Qing LUO ,  Changqing XIE ,  Ming LIU

    IPC: H03M7/30

    CPC classification number: H03M7/3062 ,  H03M7/30 ,  H04L27/2642

    Abstract: A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with fNYQ/M using M channels, and integrating sampling values of each channel to obtain M measurement values. A reconstruction end reconstructs an original signal by solving optimization problems. Based on theory, compressive sampling can be performed on a sparse signal or a signal represented in a sparse manner with a frequency much lower than the Nyquist frequency, overcoming restrictions of the typical Nyquist sampling theorem. The method can be implemented simply and decrease pressure on data collection, storage, transmission and processing.

    Abstract translation: 收集频率低于奈奎斯特频率的信号的方法包括：通过数据发送端，为输入信号选择合适的变换基矩阵，使用变换基矩阵导出信号的稀疏表示，以确定稀疏度 信号，根据稀疏度计算M个压缩采样操作，使用M个通道对fNYQ / M采样信号，并对每个通道的采样值进行积分以获得M个测量值。 重建结束通过解决优化问题重建原始信号。 基于理论，可以对稀疏信号或以稀疏方式表示的信号执行压缩采样，频率远低于奈奎斯特频率，克服典型奈奎斯特采样定理的限制。 该方法可以简单实现，减少数据收集，存储，传输和处理的压力。

    CACHE MEMORY AND METHOD OF ITS MANUFACTURE
    20.
    发明公开
    CACHE MEMORY AND METHOD OF ITS MANUFACTURE 审中-公开

    公开(公告)号：US20230245691A1

    公开(公告)日：2023-08-03

    申请号：US18004968

    申请日：2020-07-20

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Chong BI ,  Ming LIU

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/20 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

    CPC classification number: G11C11/161 ,  H10B61/22 ,  H10N50/20 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.

Patent Agency Ranking