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公开(公告)号：US20240013826A1
公开(公告)日：2024-01-11
申请号：US18251699
申请日：2021-10-13
Inventor： Guozhong Xing , Di Wang , Long Liu , Huai Lin , Ming Liu
CPC classification number: G11C11/161 , H10B61/22 , H10N50/20 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G06F17/16
Abstract: Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.
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公开(公告)号：US11776607B2
公开(公告)日：2023-10-03
申请号：US17424998
申请日：2019-01-28
Inventor： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
CPC classification number: G11C11/223 , G06N3/063 , H01L29/516 , H01L29/78391 , H10B51/20 , H10B51/30
Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
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公开(公告)号：US11641787B2
公开(公告)日：2023-05-02
申请号：US16767091
申请日：2018-03-28
Inventor： Qing Luo , Hangbing Lv , Ming Liu
Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.
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公开(公告)号：US11430385B2
公开(公告)日：2022-08-30
申请号：US17053992
申请日：2018-08-02
Inventor： Di Geng , Yue Su , Ling Li , Nianduan Lu , Ming Liu
IPC: G09G3/3233 , G09G3/3291
Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.
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15.发明授权公开(公告)号：US11189345B2
公开(公告)日：2021-11-30
申请号：US16959225
申请日：2018-01-22
Inventor： Qi Liu , Wei Wang , Sen Liu , Feng Zhang , Hangbing Lv , Shibing Long , Ming Liu
Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
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Patent Agency Ranking
公开(公告)号：US20210296579A1
公开(公告)日：2021-09-23
申请号：US17250553
申请日：2018-08-02
Inventor： Qi Liu , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu , Shengjie Zhao
IPC: H01L45/00
Abstract: The present disclosure discloses a resistive random access memory, and the resistive random access memory includes a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer includes a doped HfO2 ferroelectric thin film.
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公开(公告)号：US10608177B2
公开(公告)日：2020-03-31
申请号：US15525200
申请日：2014-12-26
Inventor： Hangbing Lv , Ming Liu , Qi Liu , Shibing Long
Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.
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公开(公告)号：US10134983B2
公开(公告)日：2018-11-20
申请号：US15546212
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.
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公开(公告)号：US20220093150A1
公开(公告)日：2022-03-24
申请号：US17424998
申请日：2019-01-28
Inventor： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
IPC: G11C11/22 , H01L27/1159 , H01L27/11597 , H01L29/51 , H01L29/78 , G06N3/063
Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
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公开(公告)号：US11245074B2
公开(公告)日：2022-02-08
申请号：US16616785
申请日：2017-05-26
Inventor： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu
Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.
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