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公开(公告)号：AU1202300A
公开(公告)日：2000-05-01
申请号：AU1202300
申请日：1999-10-08
Applicant: INTEL CORP
Inventor： MAKINENI SIVAKUMAR , KIMN SUNNHYUK , DOSHI GAUTAM B , GOLLIVER ROGER A
Abstract: A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.
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公开(公告)号：DE10195999B3
公开(公告)日：2017-05-04
申请号：DE10195999
申请日：2001-03-14
Applicant: INTEL CORP
Inventor： ELLISON CARL M , GOLLIVER ROGER A , HERBERT HOWARD C , LIN DERRICK C , MCKEEN FRANCIS X , NEIGER GILBERT , RENERIS KEN , SUTTON JAMES A , THAKKAR SHREEKANT S , MITTAL MILLIND
Abstract: Computersystem (100) mit (a) wenigstens einem Prozessor (110), der in einem normalen und in einem isolierten Ausführungsmodus betrieben werden kann, wobei der Inhalt eines Prozessorsteuerregisters (252) anzeigt, ob sich der Prozessor (110) in dem isolierten Ausführungsmodus befindet, (b) einem Systemspeicher (140) mit einem isolierten physikalischen Speicherbereich (70), auf den der Prozessor (110) nur in dem isolierten Ausführungsmodus zugreifen kann, und (c) einem mit dem Prozessor (110) und dem Systemspeicher (140) gekoppelten Chipsatz (130, 150, 160), der eine mit dem Systemspeicher (140) gekoppelte Zugriffssteuereinrichtung (135) enthält, wobei der isolierte Ausführungsmodus durch Ausführung eines privilegierten Befehls (iso_init) in dem Prozessor (110) initialisiert wird, der einen Prozessor-Nub-Lader (52) aufruft und in den isolierten Speicherbereich (70) lädt, wobei der Prozessor-Nub-Lader (52) ein in dem Chipsatz (130, 150, 160) gehaltener geschützter Bootstrap-Lader-Code ist, der ein Prozessor-Nub-Softwaremodul (18) in den isolierten Speicherbereich (70) lädt und dessen Integrität überprüft, wobei das Prozessor-Nub-Softwaremodul (18) hardwarebezogene Dienste für die isolierte Ausführung zur Verfügung stellt, wobei die Zugriffssteuereinrichtung (135) aufweist: (c1) einen von dem Prozessor (110) konfigurierbaren Konfigurationsspeicher (610), der eine den isolierten physikalischen Speicherbereich (70) definierende Konfigurationseinstellung (612) in Speicherbereichsregistern (620, 630) speichert, (c2) einen Zugriffsgewährungsgenerator (650), der bei einer Zugriffstransaktion von dem Prozessor (110) Zugriffsinformationen (660) empfängt, die eine physikalische ...
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公开(公告)号：GB2497455A
公开(公告)日：2013-06-12
申请号：GB201303912
申请日：2011-09-23
Applicant: INTEL CORP
Inventor： SAMUDRALA SRIDHAR , GOLLIVER ROGER A , MAHURIN ERIC W , WIEDEMEIER JEFF
IPC: G06F9/30
Abstract: A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
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公开(公告)号：DE19983870B4
公开(公告)日：2005-05-19
申请号：DE19983870
申请日：1999-12-08
Applicant: INTEL CORP
Inventor： MAKINENI SIVAKUMAR , KIMN SNNHYUK , DOSHI GAUTMAN B , GOLLIVER ROGER A
Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.
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公开(公告)号：GB2377795B
公开(公告)日：2004-12-01
申请号：GB0225052
申请日：2001-03-23
Applicant: INTEL CORP
Inventor： ELLISON CARL M , GOLLIVER ROGER A , HERBERT HOWARD C , LIN DERRICK C , MCKEEN FRANCIS X , NEIGER GILBERT , RENERIS KEN , SUTTON JAMES A , THAKKAR SHREEKANT S , MITTAL MILLIND
Abstract: A technique is provided to execute isolated instructions according to an embodiment of the present invention. An execution unit executes an isolated instruction in a processor operating in a platform. The processor is configured in one of a normal execution mode and an isolated execution mode. A parameter storage containing at least one parameter to support execution of the isolated instruction when the processor is configured in the isolated execution mode.
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Patent Agency Ranking
公开(公告)号：GB2378794B
公开(公告)日：2004-07-28
申请号：GB0225043
申请日：2001-03-14
Applicant: INTEL CORP
Inventor： ELLISON CARL M , GOLLIVER ROGER A , HERBERT HOWARD C , LIN DERRICK C , MCKEEN FRANCIS X , NEIGER GILBERT , RENERIS KEN , SUTTON JAMES A , THAKKAR SHREEKANT S , MITTAL MILLIND
Abstract: The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.
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公开(公告)号：GB2360110B
公开(公告)日：2003-05-21
申请号：GB0114436
申请日：1999-12-08
Applicant: INTEL CORP
Inventor： MAKINENI SIVAKUMAR , KIMN SNNHYUK , DOSHI GAUTMAN B , GOLLIVER ROGER A
Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.
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公开(公告)号：GB2377794A
公开(公告)日：2003-01-22
申请号：GB0225050
申请日：2001-03-21
Applicant: INTEL CORP
Inventor： HERBERT HOWARD C , GRAWROCK DAVID W , ELLISON CARL M , GOLLIVER ROGER A , LIN DERRICK C , MCKEEN FRANCIS X , PORSCHE AKTIENGESELLSCHAFT DR , RENERIS KEN , SUTTON JAMES A , THAKKAR SHREEKANT S , MITTAL MILLIND , NEIGER GILBERT
Abstract: In one embodiment, a method of remote attestation for a special mode of operation. The method comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing each of a plurality of IsoX software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving a remote attestation request from a remotely located platform. Then, the retrieved audit log is digitally signed to produce a digital signature for transfer to the remotely located platform.
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公开(公告)号：AU4760101A
公开(公告)日：2001-10-15
申请号：AU4760101
申请日：2001-03-21
Applicant: INTEL CORP
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公开(公告)号：GB2498466A
公开(公告)日：2013-07-17
申请号：GB201304303
申请日：2011-09-24
Applicant: INTEL CORP
Inventor： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER A
Abstract: A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.
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