公开(公告)号：GB2469373B

公开(公告)日：2011-10-19

申请号：GB201005305

申请日：2010-03-29

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV N ,  HUFFMAN AMBER D ,  BOYD JAMES A ,  HADY FRANK T ,  HINTON GLENN J ,  JUENEMANN DALE J ,  PINTO OSCAR P ,  TETRICK SCOTT R ,  BARNES THOMAS J ,  BURRIDGE SCOTT E

IPC: G06F12/08 ,  G06F12/12

Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

公开(公告)号：AU2233099A

公开(公告)日：2000-08-01

申请号：AU2233099

申请日：1999-01-15

Applicant: INTEL CORP

Inventor： KRICK ROBERT F ,  HINTON GLENN J ,  UPTON MICHAEL D ,  SAGER DAVID J ,  LEE CHAN W

IPC: G06F9/32 ,  G06F9/38 ,  G06F12/08

公开(公告)号：PL178832B1

公开(公告)日：2000-06-30

申请号：PL30747395

申请日：1995-02-28

Applicant: INTEL CORP

Inventor： BRAYTON JAMES M ,  RHODEHAMEL MICHAEL W ,  SARANGDHAR NITIN V ,  HINTON GLENN J

IPC: G06F9/38 ,  G06F12/08 ,  G06F13/18 ,  G06F13/16

Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

公开(公告)号：DE19914210A1

公开(公告)日：1999-10-07

申请号：DE19914210

申请日：1999-03-29

Applicant: INTEL CORP

Inventor： ROUSSEL PATRICE ,  HINTON GLENN J ,  THAKKAR SHREEKANT S ,  BOSWELL BRENT R ,  MENEZES KAROL F

IPC: G06F9/302 ,  G06F15/00

Abstract: A single macroinstruction is received, which specifies at least two logical registers. These registers each store first and second operands in packed data form with data elements in mutual correspondence. An operation specified from the individual macroinstructions, is executed on numbers of first and second mutually-corresponding data elements of the first and second operands, at different times, using the same circuit to produce independently, numbers of first and second resulting data elements. These are stored in a single logical register as third packed data operands. An Independent claim is included for the corresponding processor and system.

公开(公告)号：AT184407T

公开(公告)日：1999-09-15

申请号：AT94307771

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：IE80854B1

公开(公告)日：1999-04-07

申请号：IE940337

申请日：1994-04-12

Applicant: INTEL CORP

Inventor： ABRAMSON JEFFREY M ,  AKKARY HAITHAM ,  GLEW ANDREW F ,  HINTON GLENN J ,  KONIGSFELD KRIS G ,  MADLAND PAUL D

IPC: G06F9/28 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177 ,  G06F9/46

公开(公告)号：GB2281422B

公开(公告)日：1997-09-10

申请号：GB9408016

申请日：1994-04-22

Applicant: INTEL CORP

Inventor： ABRAMSON JEFFREY M ,  AKKARY HAITHAM ,  GLEW ANDREW F ,  HINTON GLENN J ,  KONIGSFELD KRIS G ,  MADLAND PAUL D

IPC: G06F9/28 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177

公开(公告)号：MX9702265A

公开(公告)日：1997-06-28

申请号：MX9702265

申请日：1995-08-24

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  HINTON GLENN J

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: Un valor de tipo de memoria que identifica el tipo de memoria contenida con un gama de ubicaciones de memoria, se almacena explícitamente dentro de un microprocesador (200-216). Antes de procesar una microinstruccion de memoria tal como una carga o un almacenamiento, el tipo de memoria se determina (214-216) para la ubicacion de memoria identifica por la microinstruccion de memoria. Una vez que el tipo de memoria se conoce, se procesa la micro-instruccion de memoria (218-230) de acuerdo con cualquiera de una cantidad de protocolos de procesamiento incluyendo procesamiento de escritura directa (220), procesamiento de escritura hacia atrás (222), procesamiento con proteccion de escritura (224), procesamiento con restringida capacidad de guardar en bancos de memoria de alta velocidad (226), procesamiento en combinacion de escritura especulable no susceptible a guardar en bancos de memoria de alta velocidad (230) o procesamiento no susceptible a guardar en bancos de memoria de alta velocidad (228).. Al proporcionar informacion explícitamente de tipo de memoria dentro del microprocesador, el protocolo por el cual se procesa la microinstruccion puede ajustarse eficientemente a la medida al tipo de memoria. En una modalidad ejemplar el microprocesador es un microprocesador fuera-de-orden (200), capaz de generar microinstrucciones de memoria especulativa (202-204).

公开(公告)号：GB2291513A

公开(公告)日：1996-01-24

申请号：GB9414028

申请日：1994-07-12

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  GLEW ANDREW F ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38

Abstract: A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions ie: still in the pipeline, for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.

公开(公告)号：DE19506990A1

公开(公告)日：1995-09-07

申请号：DE19506990

申请日：1995-02-28

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL A ,  GLEW ANDREW F ,  HINTON GLENN J ,  PAPWORTH DAVID B

IPC: C23C14/35 ,  C23C16/511 ,  G06F9/38 ,  G06F9/28

Abstract: A bypassing scheme for increasing the throughput of instructions executed by a complex microprocessor. The functional units within the execution data path are provided with bypassing multiplexer logic which allows the result data from an executed instruction to be immediately provided as source data to a dependent instruction at a different or the same execution unit. By providing comprehensive bypassing between execution units in the data path, instruction execution throughput can be maximized.