公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/768

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US11088103B2

公开(公告)日：2021-08-10

申请号：US16646084

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Xiaoying Guo ,  Aleksandar Aleksov ,  Steve S. Cho ,  Leonel Arana ,  Robert May ,  Gang Duan

IPC: H01L23/52 ,  H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20240347402A1

公开(公告)日：2024-10-17

申请号：US18756679

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Leonel Arana ,  Benjamin Duong

IPC: H01L23/13 ,  H01L23/15 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/15 ,  H01L25/0655

Abstract: Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.

公开(公告)号：US20240006327A1

公开(公告)日：2024-01-04

申请号：US17856663

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert A. May ,  Brandon Marin ,  Benjamin Duong ,  Suddhasattwa Nad ,  Hsin-Wei Wang ,  Leonel Arana ,  Darko Grujicic

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/08

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

公开(公告)号：US20230096835A1

公开(公告)日：2023-03-30

申请号：US17484519

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Bohan Shan ,  Hongxia Feng ,  Xiaoying Guo ,  Adam Schmitt ,  Jacob Vehonsky ,  Steve Cho ,  Leonel Arana

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

公开(公告)号：US20230095281A1

公开(公告)日：2023-03-30

申请号：US17484499

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Hongxia Feng ,  Xiaoying Guo ,  Steve Cho ,  Jung Kyu Han ,  Changhua Liu ,  Leonel Arana ,  Rahul Manepalli ,  Dingying Xu ,  Amram Eitan

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/488 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

公开(公告)号：US10515824B2

公开(公告)日：2019-12-24

申请号：US15868942

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Leonel Arana ,  Nicholas S. Haehn ,  Hsin-Wei Wang ,  Oscar Ojeda ,  Arnab Roy

IPC: H01L21/321 ,  H01L21/3213 ,  C23F1/14 ,  H01L21/48

Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

公开(公告)号：US11948848B2

公开(公告)日：2024-04-02

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Oscar Ojeda ,  Leonel Arana ,  Suddhasattwa Nad ,  Robert May ,  Hiroki Tanaka ,  Brandon C. Marin

IPC: H01L23/31 ,  H01L21/283 ,  H01L23/498 ,  H05K1/02 ,  H05K3/06

CPC classification number: H01L23/3114 ,  H01L21/283 ,  H05K1/0296 ,  H05K3/061

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20210375746A1

公开(公告)日：2021-12-02

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

公开(公告)号：US20210280463A1

公开(公告)日：2021-09-09

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.