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    PHYSICAL LAYER PROCESSING FOR A WIRELESS COMMUNICATION SYSTEM USING CODE DIVISION MULTIPLE ACCESS
    12.
    发明申请
    PHYSICAL LAYER PROCESSING FOR A WIRELESS COMMUNICATION SYSTEM USING CODE DIVISION MULTIPLE ACCESS 审中-公开
    使用代码段多路访问的无线通信系统的物理层处理

    公开(公告)号：WO02084889A3

    公开(公告)日：2003-04-17

    申请号：PCT/US0211811

    申请日：2002-04-16

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

    IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

    CPC classification number: H04L1/0059 ,  H03M13/09 ,  H03M13/23 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0045 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer (82). The physical channel buffer addresses (84) are determined corresponding to addresses of the bits after rate matching (88), bit scrambling (90), second interleaving (92) and physical channel mapping (94). The bits are directly read (78) from the first interleaver buffer (82) and written to the physical channel buffer (84) using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer (82) from the address of bits in the physical channel buffer (84). The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching (88), reverse bit scrambling (90), reverse second interleaving (92) and reverse physical channel mapping (94). The bits are directly read from the determined first interleaver buffer addresses (82) and written to the physical channel buffer addresses (84).

    Abstract translation: 本发明包括用于物理层处理的各种实施例。 一个实施例从第一交织器缓冲器（82）中的位的地址确定物理信道缓冲器中的比特的地址映射。 对应于速率匹配（88），比特加扰（90），第二交织（92）和物理信道映射（94）之后的比特的地址来确定物理信道缓冲器地址（84）。 从第一交织器缓冲器（82）直接读取这些比特（78），并使用确定的物理信道缓冲器地址将其写入物理信道缓冲器（84）。 另一实施例根据物理信道缓冲器（84）中的比特地址确定第一交织器缓冲器（82）中比特的地址映射。 对应于反向速率匹配（88），反向比特加扰（90），反向第二交织（92）和反向物理信道映射（94）之后的比特的地址来确定第一交织器缓冲器地址。 这些位从确定的第一交织器缓冲器地址（82）直接读取并写入物理信道缓冲器地址（84）。

    METHOD AND APPARATUS FOR ADJUSTING CHANNEL QUALITY INDICATOR FEEDBACK PERIOD TO INCREASE UPLINK CAPACITY
    13.
    发明公开
    METHOD AND APPARATUS FOR ADJUSTING CHANNEL QUALITY INDICATOR FEEDBACK PERIOD TO INCREASE UPLINK CAPACITY 审中-公开
    方法和装置适应信道质量指示符反馈的持续时间，以便提高上行链路容量

    公开(公告)号：EP1917739A4

    公开(公告)日：2009-01-07

    申请号：EP06789892

    申请日：2006-08-22

    Applicant: INTERDIGITAL TECH CORP

    Inventor： MARINIER PAUL ,  CASTOR DOUGLAS R

    IPC: H04B7/216

    CPC classification number: H04W24/10 ,  H04L1/0026 ,  H04L1/0027 ,  H04L5/0057

    Abstract: A method and apparatus for adjusting a channel quality indicator (CQI) feedback period to increase uplink capacity in a wireless communication system are disclosed. The uplink capacity is increased by reducing the uplink interference caused by CQI transmissions. A wireless transmit/receive unit (WTRU) monitors a status or downlink transmissions to the WTRU and sets the CQI feedback period based on the status of the downlink transmissions to the WTRU. A base station monitors uplink and downlink transmission needs. The base station determines the CQI feedback period of at least one WTRU based on the uplink and downlink transmission needs and sends a command to the WTRU to change the CQI feedback period of the WTRU.

    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK
    17.
    发明公开
    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK 审中-公开
    VERFAHREN UND VORRICHTUNG ZUM EFFIZIENTEN ZUTEILEN UND NEUZUTEILEN VON IN EINEM SPEICHERSTAPEL GESPEICHERTEN VERSCHACHTELTEN DATEN

    公开(公告)号：EP1751872A4

    公开(公告)日：2007-06-20

    申请号：EP05745695

    申请日：2005-05-03

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P ,  MCCLELLAN GEORGE W

    IPC: H03M7/00 ,  H04B7/00 ,  H04B7/216 ,  H04J1/00 ,  H04J3/00 ,  H04L12/56 ,  H04W28/14

    CPC classification number: H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    Abstract translation: 一种用于有效地分配和解除分配存储在存储器栈中的交织数据的方法和设备（10）。 该装置包括处理器（22）和包括至少一个存储器堆栈的存储器（12）。 处理器接收并交织多个数据块。 每个数据块被分配给特定的传输信道（TrCH）并具有指定的传输时间间隔（TTI）。 处理器基于每个数据块的TTI将交织的数据块存储在存储器堆栈中，使得具有较大TTI的数据块较早地分配给存储器堆栈并且比堆栈中从具有较小TTI的数据块更晚释放 。 在一个实施例中，存储器包括用于公共/共享上行链路信道的第一存储器栈，用于专用上行链路信道的第二存储器栈，用于公共/共享下行链路信道的第三存储器栈以及用于专用下行链路信道的第四存储器栈。

    19.
    发明专利
    未知

    公开(公告)号：DE602005015246D1

    公开(公告)日：2009-08-13

    申请号：DE602005015246

    申请日：2005-10-25

    Applicant: INTERDIGITAL TECH CORP

    Inventor： PIETRASKI PHILIP J ,  STERNBERG GREGORY S ,  CASTOR DOUGLAS R

    IPC: H04W4/00 ,  H04L1/00 ,  H04L1/20 ,  H04W24/00 ,  H04W28/04 ,  H04W28/18 ,  H04W48/08

    Abstract: A method and apparatus for adaptively biasing a channel quality indicator (CQI) used for setting a configuration of communication between a transmitter and a receiver in a wireless communication system. The receiver sends a CQI and positive acknowledgement (ACK)/negative acknowledgement (NACK) messages to the transmitter. The ACK/NACK messages indicate the absence or presence of error, respectively, in a transmitted data packet. The CQI is derived from the signal-to-interference ratio (SIR) and the ACK/NACK messages. The transmitter calculates the block error rate (BLER) of the transmitted data packets based upon the ACK/NACK messages sent from the receiver. The transmitter compares the BLER of the transmitted data packets to a target BLER and biases the CQI based on the comparison in order to achieve the target BLER.

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