公开(公告)号：US20240113007A1

公开(公告)日：2024-04-04

申请号：US17958012

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Kristof Darmawikarta ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16

Abstract: Microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. A conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. A first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.

公开(公告)号：US20240096561A1

公开(公告)日：2024-03-21

申请号：US17948586

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Benjamin Duong ,  Shayan Kaviani ,  Joshua Stacey ,  Miranda Ngan ,  Dilan Seneviratne ,  Thomas Heaton ,  Srinivas Venkata Ramanuja Pietambaram ,  Whitney Bryks ,  Jieying Kong

IPC: H01G4/33 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01L28/92 ,  H01L25/16

Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.

公开(公告)号：US20240006327A1

公开(公告)日：2024-01-04

申请号：US17856663

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert A. May ,  Brandon Marin ,  Benjamin Duong ,  Suddhasattwa Nad ,  Hsin-Wei Wang ,  Leonel Arana ,  Darko Grujicic

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/08

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

公开(公告)号：US20220084962A1

公开(公告)日：2022-03-17

申请号：US17024307

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Benjamin Duong ,  Telesphor Kamgaing ,  Miranda Ngan ,  Srinivas Pietambaram

IPC: H01L23/66 ,  H05K1/02 ,  H01P3/08 ,  H01Q1/22 ,  H01L25/065 ,  H01L25/00

Abstract: An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.

公开(公告)号：US20250112100A1

公开(公告)日：2025-04-03

申请号：US18375209

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Robert May ,  Hiroki Tanaka ,  Tarek Ibrahim ,  Lilia May ,  Jason Gamba ,  Benjamin Duong ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

公开(公告)号：US20250006781A1

公开(公告)日：2025-01-02

申请号：US18344695

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Darko Grujicic ,  Marcel Wall ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01G4/012 ,  H01L21/48 ,  H01L23/498

Abstract: Carbon nanofiber capacitor apparatus and related methods are disclosed herein. An example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. The capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.

公开(公告)号：US12057252B2

公开(公告)日：2024-08-06

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H05K1/02 ,  H01F1/37 ,  H01F17/04 ,  H01F17/06 ,  H01F27/24 ,  H01F27/245 ,  H01F27/28 ,  H01F27/29 ,  H01F41/24 ,  H01F41/32 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64 ,  H05K1/09 ,  H05K3/02 ,  H05K3/42

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

公开(公告)号：US20240219644A1

公开(公告)日：2024-07-04

申请号：US18090260

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Benjamin Duong ,  Hiroki Tanaka ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram ,  Hari Mahalingam

IPC: G02B6/35 ,  G02B6/42 ,  H01L23/498

CPC classification number: G02B6/35 ,  G02B6/4274 ,  H01L23/49816

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240111095A1

公开(公告)日：2024-04-04

申请号：US17957600

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Brandon C. Marin ,  Robert Alan May ,  Suddhasattwa Nad ,  Benjamin Duong

IPC: G02B6/122

CPC classification number: G02B6/1226

Abstract: A hybrid plasmonic waveguide and associated methods are disclosed. In one example, the electronic device includes combining an electromagnetic wave propagating in a waveguide with a high refractive index and a surface plasmon from a metal surface to create a hybrid plasmon wave in a low refractive index material separating the dielectric waveguide and metal surface. In selected examples, surface mounted hybrid plasmonic waveguides are shown. In selected examples hybrid plasmonic waveguides embedded in glass interposers are shown.