公开(公告)号：JP2001168275A

公开(公告)日：2001-06-22

申请号：JP2000322417

申请日：2000-10-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L25/18 ,  H01L21/301 ,  H01L21/304 ,  H01L21/60 ,  H01L23/04 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide a method for lowering the height of a whole IC package in technology for manufacturing the IC package. SOLUTION: The method includes a step for thinning the IC device of a chip form. It is realized in the final stage of assembly, in which a chip is flip chip-fixed to a substrate, and the backside of the chip is exposed due to thinning. When the method is used, the chip of which final thickness is about 2 to 8 mils can be manufactured and the whole thickness of the package is considerably reduced.

公开(公告)号：JPH11345932A

公开(公告)日：1999-12-14

申请号：JP13917599

申请日：1999-05-19

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS DIXON ,  TAI KING L

IPC: H05K1/14 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-silicon mutual connection package which is free from being affected by thermal expansion of a mutual connection package. SOLUTION: An integrated circuit package has a main printed circuit board 24, at least two intermediate printed circuit boards 15 loaded on the surface of the circuit board 24, and silicon-on-silicon multichip modules 11, 12 each of which is joined with one of the circuit boards 15 by solder junction 18. In this case, each multichip module has a silicon made integrated circuit chip 13 joined with a silicon made mutual connection substrate 14 and the thermal expansion coefficients of the main printed circuit board 24, and the intermediate printed circuit boards 15 are respectively

公开(公告)号：JPH11330164A

公开(公告)日：1999-11-30

申请号：JP6412499

申请日：1999-03-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  TAI KING L

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/18 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To avoid bleeding of solder bumps into the through-hole on double- surface circuit substrate and to perform the effective utilization of the mutually connected region, by filling the solder material which has high melting point prior to bonding the solder bump into the plated through-hole. SOLUTION: When solder is melted in bonding process at the time the double- surface substrate is bonded to a substrate with solder in solder-bump bonding and the solder is melted in the bonding process, the problem of solder bleeding occurs, and the strain and the breakdown of the solder bump occur. Then, the through-hole is covered with a solder mask. As a result, the solder bump is heated, the solder is melted, the bonding is affected, the air sealed in the through-hole is expanded and the solder bump is blown out. Therefore, when the through-hole is completely filled with solder material, the bleeding of the solder bump into the through-hole can be avoided.

公开(公告)号：JPH1116940A

公开(公告)日：1999-01-22

申请号：JP14477898

申请日：1998-05-26

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L21/60 ,  H01L21/822 ,  H01L23/488 ,  H01L23/498 ,  H01L23/556 ,  H01L25/04 ,  H01L25/18 ,  H01L27/04 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To protect I/O lead wires from an obstacle due to alpha particles by a method wherein memory chips are respectively provided with a semiconductor charge storage site, the soldered interconnection of the memory chips with a substrate for interconnection use is made within a specified value from the charge storage sites and a solder material has a specified lead content. SOLUTION: A plurality of bonded semiconductor chips 12, 13 and 14 are provided on a substrate 11 for interconnection use. The chips 12 and 13 are memory chips and the chip 14 is a logic chip. The memory chips 12 and 13 are respectively provided with a semiconductor charge storage site and are mounted on the substrate 11 using a soldered connection. The soldered interconnection of the chips 12 and 13 with the substrate 11 is made within the extent of at least 5 mills, that is, 0.127 mm, from the semiconductor charge storage sites. Moreover, the lead content of a solder material is less than 5%. As a solder to be used for bonding the chips 12 and 13 to the substrate 11 in such a way, one hardly contains an alpha particle radioactive material is used.

公开(公告)号：JP2002043449A

公开(公告)日：2002-02-08

申请号：JP2001151776

申请日：2001-05-22

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: B81C3/00 ,  B81B7/00 ,  H01L23/02 ,  H01L23/06 ,  H01L31/02

Abstract: PROBLEM TO BE SOLVED: To provide a packaging technology for a MEMS assembly where a MEMS device array is mounted on a silicon wafer platform. SOLUTION: A silicon chamber may is sealed airtightly. By using a package made of only silicon for the MEMS device array, the thermodynamic instability disappears substantially. The mechanical instability is also reduced by using a contact pin array in order to interconnect a silicon supporting substrate for the MEMS device to the next interconnection level. The MEMS device can be detached easily by using the contact pin array for the purpose of replacement or repairing.

公开(公告)号：JP2002036200A

公开(公告)日：2002-02-05

申请号：JP2001170687

申请日：2001-06-06

Applicant: LUCENT TECHNOLOGIES INC ,  AGERE SYST OPTOELECTRONICS

Inventor： DEGANI YINON ,  DUDDERAR THOMAS DIXON ,  TAI KING L

IPC: G02B26/08 ,  B81B7/00 ,  B81B7/02

Abstract: PROBLEM TO BE SOLVED: To provide the interconnection of a micro electronic machine mechanical system MEMS. SOLUTION: A conventional MEMS device array has a number of mechanical devices respectively driven by a multi chip module MCM. By mounting the multi chip modules MCM on both faces of a system interconnection board, the interconnection of high density can be achieved. The multi chip modules MCM on a common circuit for driving a predetermined mechanical element are mounted on both faces of the system interconnection board, and interconnected to each other by vias penetrating through the board, whereby the total length of interconnection is reduced. By mounting all functional elements onto a socket by using a contact pin array for electric connection, the quick replacement/repairing can be easily executed. The in-service reliability can be obtained by providing a spare socket for the redundant MCM.

公开(公告)号：JP2001116797A

公开(公告)日：2001-04-27

申请号：JP2000233853

申请日：2000-08-02

Applicant: LUCENT TECHNOLOGIES INC

Inventor： AHLQUIST LOUIS NELSON ,  DEGANI YINON ,  JACALA JERICHO J ,  KOSSIVES DEAN PAUL ,  TAI KING L

IPC: G01R31/26 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a tester for testing individual IC devices or wafers in which a pressure required for bringing all solder bumps in an IC array into contact with a test array can be reduced significantly. SOLUTION: The tester has a flat test bed comprising a socket array for containing an IC solder ball array and the socket in the test bed has a sidewall directing inward. Consequently, the socket has a sharp edge touching the solder bump array contrary to the flat or dish-like surface at a conventional recess. Since deformation required for bringing all solder bumps in the array into reliable contact with a test array can be reduced significantly, a force required for causing deformation can be reduced correspondingly.

公开(公告)号：JP2001116796A

公开(公告)日：2001-04-27

申请号：JP2000233852

申请日：2000-08-02

Applicant: LUCENT TECHNOLOGIES INC

Inventor： AHLQUIST LOUIS NELSON ,  DEGANI YINON ,  JACALA JERICHO J ,  KOSSIVES DEAN PAUL ,  TAI KING L

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H01L21/60 ,  H01R33/76 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a tester and a testing method for IC device or solder ball of a wafer in which a pressure required for bringing all solder bumps in an IC array into contact with a test array is reduced significantly. SOLUTION: Solder balls in an array are reshaped such that the contact faces of all solder balls in the array are flush with each other thus providing a uniform offset between the contact face of the solder ball and an IC board. The reshaped solder ball has cross-section of truncated sphere or has a plane on top of a sphere. The solder ball array is suitable for coming into contact with a planar test bed, for bonding to an interconnection board or for mounting on a tester having a recessed socket.

公开(公告)号：JP2000091462A

公开(公告)日：2000-03-31

申请号：JP25301799

申请日：1999-09-07

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES ,  TAI KING L

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To mutually wire one IC chip with a translator and obtain high mutual wiring density by a power source and an installation mutual wiring structure, using a power source step and a grounding step made in an isolated multistep structure mutual wiring translator. SOLUTION: A power source and a grounding step are provided with several- step isolated mutual wiring steps 31 to 34 on a translator 21 which is silicon. By a multistep structure mutual wiring feature included in the translator 21, several power source and grounding mutual wiring are adjusted and integrated by this board step. Then, a power source input/output or a grounding input/ output is further coupled to a next board step. Moreover, since the translator 21 accommodates a single multipin IC chip, it is made larger than the IC chip. This large translator region enables leading a pattern and developing it in all direction on the translator 21 made of silicon.

公开(公告)号：JPH1041350A

公开(公告)日：1998-02-13

申请号：JP11067997

申请日：1997-04-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  GREENBERG LAWRENCE ARNOLD

IPC: H01L21/56 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To provide a superior integrated circuit bonding technique which can realizes a comparatively quick and efficient method for removing flux residues and forming filled parts. SOLUTION: A contact pad 20 on the surface 15 of a board 10 is positioned to a contact pad 100 of an IC chip 1. The board 10 has holes 30 in a mounting region to mount the chip 1. An interconnection 110 is formed between the pad 100 of the chip 1 and pad 20 of the board 10, thus forming an element assembly 130. A flux cleaning fluid or filler epoxy is well fed into a low-profile gap 140 through the hole 30. The hole 30 is suited for the low-profile gap 140 of about 300 microns or less.