公开(公告)号：WO2011094477A3

公开(公告)日：2011-11-24

申请号：PCT/US2011022837

申请日：2011-01-28

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  GIMMEL PHILIPPE ,  BUDAES MARIUS ,  LEONESCU DANIEL ,  CLEVELAND TERRY ,  DEARBORN SCOTT

Inventor： DEVAL PHILIPPE ,  GIMMEL PHILIPPE ,  BUDAES MARIUS ,  LEONESCU DANIEL ,  CLEVELAND TERRY ,  DEARBORN SCOTT

IPC: H02M3/158 ,  G01R19/00

CPC classification number: H02M3/158 ,  G01R19/0092 ,  H02M2001/0009

Abstract: A high voltage switching regulator has significantly reduced current sensing delay between measurement of input current and generation of sensed current values, while maintaining good accuracy of the current through a power transistor using current replication and a current conveyor. High sensing accuracy of the input current ensures good load regulation, and low sensing delay ensures fixed duty cycle over a wide range of output currents and high input to output voltage ratios. A current conveyor is used to transfer high side current values to low side control circuits, e.g., pulse width modulation (PWM) control. The current conveyor is always on, e.g., some current flow is always present, thus minimizing any current measurement delay. This is accomplished by dynamically biasing the current conveyor by draining to ground a current equal to the sensed current. Wherein balancing of the current conveyor is ensured and offset at the input of the current conveyor is minimized.

Abstract translation: 高压开关稳压器在测量输入电流和产生感测电流值之间显着降低了电流感测延迟，同时通过使用电流复制和电流传送器保持通过功率晶体管的电流的高精度。 输入电流的高检测精度确保良好的负载调整率，低感应延迟确保在宽范围的输出电流和高输入输出电压比下的固定占空比。 电流传送器用于将高侧电流值传送到低侧控制电路，例如脉宽调制（PWM）控制。 电流传送器始终打开，例如，总是存在一些电流，从而使任何电流测量延迟最小化。 这是通过将电流传送器通过消耗等于感测电流的电流而动态偏置来实现的。 其中确保电流传送器的平衡并且使电流传送器的输入处的偏移最小化。

公开(公告)号：WO2010048371A3

公开(公告)日：2010-07-08

申请号：PCT/US2009061617

申请日：2009-10-22

Applicant: MICROCHIP TECH INC ,  QUIQUEMPOIX VINCENT ,  DEVAL PHILIPPE

Inventor： QUIQUEMPOIX VINCENT ,  DEVAL PHILIPPE

IPC: H03M3/00

CPC classification number: H03M3/34 ,  H03M3/424 ,  H03M3/456 ,  H03M3/464

Abstract: A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a.switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.

Abstract translation: 多位数字 - 模拟转换器具有参考电压发生器，其产生具有偏移电压的参考电压; 开关电容器级，用于产生多个输出电压; 以及切换定序器，其控制所述开关电容器级可操作以针对每个输出电压生成开关模式，其中每个模式具有充电阶段和传输阶段，并且其中对于至少一个输出电压，所述开关定序器提供两个开关模式，其中每个开关模式 造成相反极性的偏移。

公开(公告)号：ES2622145T3

公开(公告)日：2017-07-05

申请号：ES09741547

申请日：2009-10-22

Applicant: MICROCHIP TECH INC

Inventor： DEVAL PHILIPPE ,  QUIQUEMPOIX VINCENT ,  BARRETO ALEXANDRE

IPC: H03M3/04

Abstract: Un aparato para la reducción de los tonos de inactividad no deseados mediante la adición de una señal aleatoria a una señal digital en un convertidor de digital a analógico Sigma-Delta de bit múltiple (DAC), que comprende: un modulador de bits múltiples Sigma-Delta (202; 502) que tiene una entrada y una salida de señal digital (212; 512), el modulador Sigma-Delta de bit múltiple (202; 502) comprendiendo: un filtro de bucle digital (110; 510) que recibe la señal de entrada digital, y que convierte la señal a palabras digitales de L bit en secuencia; y el cuantificador de resolución variable (208; 508) que recibe las palabras digitales de L bit en una secuencia y que emite una palabra digital respectiva de M bit; en donde M > 1 y L > M; el aparato comprendiendo además un convertidor de digital a analógico de bit múltiple (DAC) que tiene una salida analógica y una entrada digital que recibe la palabra digital respectiva de M bit; y un filtro analógico de paso bajo (106; 105) que tiene una entrada analógica acoplada a la salida analógica del DAC de bit múltiple; el filtro de paso bajo analógico emite una señal de salida analógica respectiva; el aparato se caracteriza porque, el modulador de múltiples bits sigma delta (202; 502) comprende además un generador de secuencia aleatoria (214; 514), el generador de secuencia aleatoria (214; 514) genera una pluralidad de números aleatorios N(n) en una secuencia, en donde cada número aleatorio N(n) es un número entero aleatorio entre 1 y M; y el cuantificador de resolución variable (208; 508) se controla por el generador de secuencia aleatoria (214; 514) y adaptado para reducir la resolución de la palabra digital respectiva de L bit a una palabra digital respectiva de N(n) bits en función del respectivo número aleatorio N(n); y cuando M es mayor que el respectivo número aleatorio N(n), añadir M-N(n) bits menos significativos, comprendiendo cada uno un cero, a esta palabra digital respectiva de N(n) bits para generar la palabra de M-bit respectiva.

公开(公告)号：AT540461T

公开(公告)日：2012-01-15

申请号：AT08852419

申请日：2008-11-21

Applicant: MICROCHIP TECH INC

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：DE602005018004D1

公开(公告)日：2010-01-14

申请号：DE602005018004

申请日：2005-04-29

Applicant: MICROCHIP TECH INC

Inventor： QUIQUEMPOIX VINCENT ,  DEVAL PHILIPPE

IPC: H03M3/00

Abstract: The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.

公开(公告)号：AT450929T

公开(公告)日：2009-12-15

申请号：AT05741872

申请日：2005-04-29

Applicant: MICROCHIP TECH INC

Inventor： QUIQUEMPOIX VINCENT ,  DEVAL PHILIPPE

IPC: H03M3/00

Abstract: The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.

公开(公告)号：AT413724T

公开(公告)日：2008-11-15

申请号：AT04754523

申请日：2004-06-07

Applicant: MICROCHIP TECH INC

Inventor： DEVAL PHILIPPE ,  KAYAL MAHER ,  VAUCHER FABIEN

IPC: H03F3/45

Abstract: An electronic amplifier circuit comprising an operational amplifier circuit, such as a two-stage operational amplifier circuit, in tandem with a operational transconductance amplifier. The electronic amplifier circuit has high open-loop gain and high gain-bandwidth while maintaining stability over a wide range of operating parameters.

公开(公告)号：WO2010048360A3

公开(公告)日：2010-06-24

申请号：PCT/US2009061597

申请日：2009-10-22

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  QUIQUEMPOIX VINCENT ,  BARRETO ALEXANDRE

Inventor： DEVAL PHILIPPE ,  QUIQUEMPOIX VINCENT ,  BARRETO ALEXANDRE

IPC: H03M3/00

CPC classification number: H03M3/33 ,  H03M3/424

Abstract: A multi-bit (M-bit, M> 1 ) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract translation: 多位（M位，M> 1）或多级（nlev级，nlev> 2，在M位编码，M = Floor（log2（nlev）））Σ-Δ模数转换器 ADC）具有可变分辨率多位量化器，其具有其具有随机或伪随机序列N（n）的每个电压采样的分辨率（不同输出电平的数量）和相关联的量化阈值，以提供用于去除不期望的空闲的自动动态抖动 Σ-ΔADC的数字输出中的音调。 2和nlev之间的随机整数N（n）可以由随机或伪随机序列发生器提供，例如与数字比较器和加法器组合的Galois线性反馈移位寄存器。

公开(公告)号：WO2010048362A3

公开(公告)日：2010-06-17

申请号：PCT/US2009061599

申请日：2009-10-22

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  QUIQUEMPOIX VINCENT ,  BARRETO ALEXANDRE

Inventor： DEVAL PHILIPPE ,  QUIQUEMPOIX VINCENT ,  BARRETO ALEXANDRE

IPC: H03M3/04

CPC classification number: H03M3/33 ,  H03M3/424

Abstract: A multi-bit (M-bit, M>1 ) Sigma-Delta digital-lo-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M-N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital trunealor or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract translation: 具有可变分辨率多位量化器的多位（M位，M> 1）Σ-Δ数模转换器（DAC），其数字值输入被截断或舍入为 随机或伪随机序列，以提供自动动态抖动以消除Sigma-Delta DAC的模拟输出中的不需要的空闲音调。 提供1和M之间的随机数N（n），并且量化器的输出处的每个M位数字值中的M-N（n）个最低有效位用数字真空或舍入器强制为零。 随机数N（n）可以由随机或伪随机序列发生器提供，例如与数字比较器和加法器组合的伽罗瓦线性反馈移位寄存器。

公开(公告)号：WO2009067672A3

公开(公告)日：2009-07-09

申请号：PCT/US2008084362

申请日：2008-11-21

Applicant: MICROCHIP TECH INC ,  DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

Inventor： DEVAL PHILIPPE ,  BESSEUX PATRICK ,  YACH RANDY

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract translation: 器件接口的自适应静电放电（ESD）保护在处理或安装到系统或从系统中移除时具有良好的ESD稳健性。 并且在系统中运行时，对DPI，电磁干扰（EMI）等具有强大的抗干扰能力。 在ESD保护金属氧化物半导体（MOS）器件的漏极和栅极之间存在显着的电容耦合，以在外部连接上没有（或低电平）DPI需要保护的情况下增强ESD保护并降低其回击电压 。 因此，当在外部连接上检测到显着的DPI / EMI信号时，MOS ESD保护装置的漏极和栅极之间的电容耦合被断开，旁路或衰减，从而增强了装置的DPI / EMI抗干扰性。