公开(公告)号：SG11201701990SA

公开(公告)日：2017-05-30

申请号：SG11201701990S

申请日：2015-09-04

Applicant: QUALCOMM INC

Inventor： KIM DONG WOOK ,  WE HONG BOK ,  LEE JAE SIK ,  GU SHIQUN

IPC: H01L23/498

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

公开(公告)号：BRPI0914631A2

公开(公告)日：2015-10-20

申请号：BRPI0914631

申请日：2009-06-19

Applicant: QUALCOMM INC

Inventor： NOWAK MATTHEW ,  GU SHIQUN ,  TOMS THOMAS R

IPC: H01L23/38 ,  H01L25/065

公开(公告)号：ES2395697T8

公开(公告)日：2014-11-17

申请号：ES09700850

申请日：2009-01-08

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  KANG SEUNG ,  NOWAK MATTHEW

IPC: H01L43/08 ,  H01L43/12

公开(公告)号：CA2710334C

公开(公告)日：2013-12-10

申请号：CA2710334

申请日：2008-12-19

Applicant: QUALCOMM INC

Inventor： ZHU XIAOCHUN ,  GU SHIQUN ,  LI XIA ,  KANG SEUNG H

IPC: G11C11/16

Abstract: In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path (102) coupled to the MTJ structure and a write path (104) coupled to the MTJ structure. The write path (104) is separate from the read path (102). The device in substance comprises a pair of serially coupled MTJ structures (106, 108), whereby the read path (102) comprises only one of the MTJ structure (108). This provides for combined improved read margin and improved write margin.

公开(公告)号：ES2829898T3

公开(公告)日：2021-06-02

申请号：ES13703655

申请日：2013-01-12

Applicant: QUALCOMM INC

Inventor： RAMACHANDRA VIDHYA ,  GU SHIQUN

IPC: H01L21/768 ,  H01L23/48

Abstract: Una oblea de semiconductor (400), que comprende: un sustrato (102); una capa de dieléctrico (106) formada en un primer lateral del sustrato; y una cavidad de vía a través de sustrato (134) que se extiende a través de la capa de dieléctrico y parcialmente a través del sustrato, una capa de aislamiento (140) depositada dentro de la cavidad de vía a través de sustrato, comprendiendo la capa de aislamiento una porción con estrechamiento progresivo (142); y caracterizada por una capa de fotorresistencia (180) en la parte inferior de la cavidad de vía a través de sustrato para proteger la capa de aislamiento en la parte inferior de la cavidad de vía a través de sustrato durante la formación de la porción con estrechamiento progresivo de la capa de aislamiento mediante grabado.

公开(公告)号：ES2796653T3

公开(公告)日：2020-11-27

申请号：ES09770821

申请日：2009-06-19

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  NOWAK MATTHEW ,  TOMS THOMAS R

IPC: H01L25/065 ,  H01L23/38 ,  H01L23/48

Abstract: Un dispositivo de IC apilado (30) que comprende: un nivel superior (11) y un nivel inferior (12), teniendo cada nivel una capa de sustrato y una capa activa en la que están dispuestos unos circuitos activos, en el que el nivel superior (11) y el nivel inferior (12) están apilados de modo que la capa activa (102) del nivel superior está enfrente de la capa activa (103) del nivel inferior; y un dispositivo termoeléctrico (TE) que comprende al menos una unión P-N (301, 302) y un conductor inferior (303), en el que el material de la unión P-N está dispuesto dentro de la capa de sustrato (101) del nivel superior, en el que el dispositivo TE está adaptado para facilitar un flujo térmico entre el conductor inferior de dicho dispositivo TE y un área localizada (110) del dispositivo de IC apilado (30), y en el que el flujo térmico pasa a través de las capas activas de los niveles superior e inferior.

公开(公告)号：HUE049459T2

公开(公告)日：2020-09-28

申请号：HUE09770821

申请日：2009-06-19

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  NOWAK MATTHEW ,  TOMS THOMAS R

IPC: H01L23/38 ,  H01L23/48

公开(公告)号：CA3031207A1

公开(公告)日：2018-02-15

申请号：CA3031207

申请日：2017-07-17

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  ZUO CHENGJIE ,  FANELLI STEVE ,  MASARACIOGLU HUSNU AHMET

IPC: H01L23/31 ,  H01L21/60 ,  H01L23/538

Abstract: A package (300) includes a redistribution portion (302), a first portion (204), and a second portion (206). The first portion is coupled to the redistribution portion. The first portion includes a first switch (241) comprising a plurality of switch interconnects (245), and a first encapsulation layer (240) that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters (261). Each filter includes a plurality of filter interconnects (265). The second portion also includes a second encapsulation layer (260) that at least partially encapsulates the first plurality of filters. The first portion includes a second switch (243) positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters (263) positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters.

公开(公告)号：CA2735689C

公开(公告)日：2016-06-21

申请号：CA2735689

申请日：2009-09-01

Applicant: QUALCOMM INC

Inventor： KASKOUN KENNETH ,  GU SHIQUN ,  NOWAK MATTHEW

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/60

Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semi-conductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.

公开(公告)号：CA2726476C

公开(公告)日：2016-05-24

申请号：CA2726476

申请日：2009-06-19

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  NOWAK MATTHEW ,  TOMS THOMAS R

IPC: H01L25/065 ,  H01L23/38

Abstract: Thermal conductivity in a stacked IC device (30) can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices (300) can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions (301, 302) created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.