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    11.
    发明专利
    未知

    公开(公告)号：DE69321245D1

    公开(公告)日：1998-10-29

    申请号：DE69321245

    申请日：1993-12-29

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).

    15.
    发明专利
    未知

    公开(公告)号：DE69312305D1

    公开(公告)日：1997-08-21

    申请号：DE69312305

    申请日：1993-12-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07

    Abstract: A voltage booster (1) comprising a charge pump (2) for generating a boost voltage (Vboost) over a boost line (3). The booster comprises a comparator (6) which is supplied by a voltage divider (5) with a voltage V1 proportional to the boost voltage (Vboost), and by a reference source (4) with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump (2). A voltage limiter (8) is connected between the boost line (3) and ground; and a boost circuit (7) accelerates the voltage increase on the boost line following low-power operation in which the paths toward ground are interrupted for reducing consumption.

    18.
    发明专利
    未知

    公开(公告)号：DE69026828D1

    公开(公告)日：1996-06-05

    申请号：DE69026828

    申请日：1990-12-13

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI

    IPC: G11C17/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/56 ,  G11C7/00

    Abstract: The sense circuit, for recognizing the virgin or programmed status of cells in storage devices, comprises a differential amplifier (DA) having a first input (Xo) connected to a number of selectable matrix cells (Tvm, Tpm) through a first uncoupling circuit (INVc, Tcu), a second input (Yo) connected to a number of selectable reference virgin cells (Tvr1, Tvr2) through a second uncoupling circuit (INVR, Tru), respective matrix and reference load transistors (TCL, TRL) connected between each input of the amplifier and a supply voltage, and a current generator (Ts, Tb, To) connected in parallel to the matrix cells and controlled by the first input of the amplifier to draw a current equal to a predetermined fraction of the current flowing through said first input.

    19.
    发明专利
    未知

    公开(公告)号：DE69109521T2

    公开(公告)日：1996-03-14

    申请号：DE69109521

    申请日：1991-02-07

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: H03K3/354 ,  H02M3/07

    Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

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