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    14.
    发明专利
    未知

    公开(公告)号：DE69808711T2

    公开(公告)日：2003-08-14

    申请号：DE69808711

    申请日：1998-08-28

    Applicant: SONY CORP

    Inventor： NAKAJIMA YOSHIHARU ,  MAEKAWA TOSHIKAZU

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

    Abstract: A liquid crystal display device having output buffers (16-1, ..., 16-n) corresponding to column lines (20-1, ..., 20-n), comprises analog switches (18-1, ..., 18-n) provided between output ends of the output buffers (16-1, ..., 16-n) and the column lines (20-1, ..., 20-n) respectively, and a switch controller (19) for on-off controlling the analog switches (18-1, ..., 18-n). A DA converter (15) is provided in the preceding stage of the output buffers (16-1, ..., 16-n), and the switch controller (19) turns off the analog switches (18-1, ..., 18-n) during a DA conversion period of the DA converter (15) or during a precharge period prior to DA conversion, and turns on the analog switches (18-1, ..., 18-n) during a predetermined period other than such periods.

    15.
    发明专利
    未知

    公开(公告)号：DE69804067D1

    公开(公告)日：2002-04-11

    申请号：DE69804067

    申请日：1998-09-09

    Applicant: SONY CORP

    Inventor： MAEKAWA TOSHIKAZU

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H01L29/786

    Abstract: In an active matrix type LCD having a driving circuit unit which is capable of accepting digital signals having a signal level lower than the power source voltage of a horizontal driving circuit system combined with pixel unit, level shift circuits (15-1 to 15-n) for converting the level of sampled digital signals having a small amplitude to digital signals having a voltage of 0 to the power source voltage Vd are provided between sampling switches (12-1 to 12-n) and latch circuits (16-1 to 16-n). The structure is thus capable of accepting from the outside digital signals having a small signal amplitude and can be applied to a medium to large sized LCD.

    16.
    发明专利
    未知

    公开(公告)号：DE69517552T2

    公开(公告)日：2001-02-08

    申请号：DE69517552

    申请日：1995-04-21

    Applicant: SONY CORP

    Inventor： MAEKAWA TOSHIKAZU

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36

    Abstract: The active matrix display device has a plurality of gate lines X provided on horizontal lines, a plurality of data lines Y provided on vertical lines, and a plurality of picture elements PXL provided at each intersection of both lines. The picture elements PXL provided horizontally and vertically constitute the display region 1. The vertical scanning circuit 2 scans vertically each gate line X sequentially, and selects picture elements on a respective one horizontal line every one horizontal period. The horizontal scanning circuit 3 scans each data line Y sequentially in one horizontal period, samples image signal Vsig, and writes by dot sequential scanning the image signal Vsig on picture elements PXL of a respective selected horizontal line. The data lines are defined in two sections, real data lines Y1, Y2, ...,YL provided in the display region 1, and dummy data lines YD1, YD2, YD3, and YD4 provided outside the display region, which dummy data lines intersect with the end section of the gate lines. The horizontal scanning circuit 3 scans horizontally the real data lines Y1, Y2,...,YL with a sampling timing overlapping a plurality of the real data lines, subsequently continues to scan the dummy data lines YD1, YD2, YD3 and YD4 with the overlapped sampling timing. Thereby, a band defect usually appearing on the side end of the screen when an active matrix display device is driven dot sequentially, is eliminated.

    17.
    发明专利
    未知

    公开(公告)号：DE69512301T2

    公开(公告)日：2000-03-23

    申请号：DE69512301

    申请日：1995-04-21

    Applicant: SONY CORP

    Inventor： MAEKAWA TOSHIKAZU

    IPC: G02F1/133 ,  G09G3/36 ,  G11C7/10 ,  G11C8/04 ,  G11C19/00 ,  H04N3/12 ,  H04N3/27 ,  H04N5/66

    Abstract: An active matrix display device comprises a plurality of pixels, a vertical scanning circuit, a horizontal addressing circuit, a wide input switch element and a normal input switch element. The plurality of pixels are arrayed in a matrix shape. The vertical scanning circuit sequentially selects pixels every line. The horizontal addressing circuit dot-sequentially addresses selected line pixels and has a shift register constituted by a number of multi-stage connected flip-flops, the number of which corresponds to the total number of rows of pixels. Each flip-flop is equipped with a pair of input/output terminals and a prescribed start pulse is transferred every stage. The wide input switch element inputs a start pulse to an input terminal of a flip-flop positioned at a leading stage during wide displaying. The normal input switch element inputs a start pulse to an input of a flip-flop positioned at a specific intermediate stage during normal displaying. It is therefore possible to switch over between a wide display and a normal display using a horizontal addressing circuit employing a single shift register.

    18.
    发明专利
    未知

    公开(公告)号：DE69416041D1

    公开(公告)日：1999-03-04

    申请号：DE69416041

    申请日：1994-06-29

    Applicant: SONY CORP

    Inventor： MAEKAWA TOSHIKAZU

    IPC: G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H04N3/12 ,  H04N5/44 ,  H04N5/70

    Abstract: An active matrix display device is disclosed which realizes changing over between a wide display and a normal display with a simple construction. The active matrix display device includes picture elements disposed in rows and columns on a horizontally elongated screen. A gate line is connected to each picture element row while a data line is connected to each picture element column. A signal line for supplying a video signal and data lines are connected by way of sampling switches. A horizontal shift register controls sequential opening and closing operations of the sampling switches. The picture element columns of the horizontally elongated screen are divided into a predetermined area allocated to a normal display and a pair of expansion areas included in a wide display. The horizontal shift register is divided into a predetermined stage section corresponding to the predetermined area and expansion stage sections corresponding to the expansion areas. Upon wide display, the predetermined and expansion stage sections of the horizontal shift register are interconnected serially into an integrated condition, but upon normal display, the expansion stage sections are disconnected from the predetermined stage section.

    SIGNAL TRANSLATING CIRCUIT
    19.
    发明专利
    SIGNAL TRANSLATING CIRCUIT 未知

    公开(公告)号：CA1230651A

    公开(公告)日：1987-12-22

    申请号：CA435542

    申请日：1983-08-29

    Applicant: SONY CORP

    Inventor： SONEDA MITSUO ,  MAEKAWA TOSHIKAZU ,  OTSU KOUJI

    IPC: G09G3/36 ,  G09G3/22 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H03K5/15 ,  H04N3/14

    Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.

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