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    11.
    发明专利
    未知

    公开(公告)号：FR2779573B1

    公开(公告)日：2001-10-26

    申请号：FR9807061

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  REGOLINI JORGE LUIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732

    Abstract: The bipolar transistor comprises a base (Be) of heterojunction silicon-germanium. The base is in block (8) of layers of silicon and silicon-germanium on an initial layer (17) of silicon nitride spread on a region with lateral isolation (5). An internal collector (4) is enclosed and situated inside a window in the layer of silicon nitride. The fabrication process includes the growth of a layer of silicon dioxide on a block of semiconductor. A layer of silicon nitride (Si3N4) is then deposited, and etched until the layer of silicon dioxide. A chemical process is used to remove a portion of the layer of silicon dioxide within the window. The layer of silicon nitride has a thickness of about 300 Angstrom, and that of silicon dioxide about 200 Angstrom.

    12.
    发明专利
    未知

    公开(公告)号：FR2805923A1

    公开(公告)日：2001-09-07

    申请号：FR0002855

    申请日：2000-03-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L21/331

    Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

    13.
    发明专利
    未知

    公开(公告)号：FR2858877B1

    公开(公告)日：2005-10-21

    申请号：FR0350418

    申请日：2003-08-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTINET BERTRAND ,  MARTY MICHEL ,  CHEVALIER PASCAL ,  CHANTRE ALAIN

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

    TRANSISTOR BIPOLAIRE A BASE EXTRINSEQUE MONOCRISTALLINE ISOLEE DU COLLECTEUR
    14.
    发明专利
    TRANSISTOR BIPOLAIRE A BASE EXTRINSEQUE MONOCRISTALLINE ISOLEE DU COLLECTEUR 未知

    公开(公告)号：FR2868206A1

    公开(公告)日：2005-09-30

    申请号：FR0450609

    申请日：2004-03-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  CHEVALIER PASCAL

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732

    Abstract: L'invention concerne un transistor bipolaire réalisé dans un substrat semiconducteur (20) d'un premier type de conductivité, comportant, directement sur le substrat, une région semiconductrice monocristalline (34) dopée d'un second type de conductivité délimitée par un isolant (30) et immédiatement sous-jacente à une couche semiconductrice monocristalline (26) dopée du second type de conductivité constituant la base extrinsèque du transistor, ladite base extrinsèque monocristalline s'étendant également sur ledit isolant, un émetteur (19) du transistor étant formé sur ladite région semiconductrice monocristalline et étant isolé de ladite base extrinsèque monocristalline.

    15.
    发明专利
    未知

    公开(公告)号：FR2779572B1

    公开(公告)日：2003-10-17

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

    17.
    发明专利
    未知

    公开(公告)号：FR2779571B1

    公开(公告)日：2003-01-24

    申请号：FR9807060

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L21/266

    Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

    18.
    发明专利
    未知

    公开(公告)号：FR2805923B1

    公开(公告)日：2002-05-24

    申请号：FR0002855

    申请日：2000-03-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L21/331

    Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

    DISPOSITIF LASER ET PROCEDE DE FABRICATION D’UN TEL DISPOSITIF LASER
    19.
    发明专利
    DISPOSITIF LASER ET PROCEDE DE FABRICATION D’UN TEL DISPOSITIF LASER 未知

    公开(公告)号：FR3043852A1

    公开(公告)日：2017-05-19

    申请号：FR1560911

    申请日：2015-11-13

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： FERROTTI THOMAS ,  BEN BAKIR BADHISE ,  CHANTRE ALAIN ,  CREMER SEBASTIEN ,  DUPREZ HELENE

    IPC: H01S5/187

    Abstract: L'invention concerne un dispositif laser (1) disposé dans et/ou sur silicium et à hétéro structure III-V comprenant - un milieu amplificateur (3) à hétérostructure III-V, et - un guide d'onde optique en arête (11), disposé en regard du milieu amplificateur (3) et comprenant un guide d'onde en ruban (15) doté d'une arête longitudinale (17), le guide d'onde optique en arête (11) étant disposé dans du silicium, - deux réseaux de Bragg échantillonnés (RBE-A, RBE-B) formés dans le guide d'onde optique en arête (11) et disposés de part et d'autre par rapport au milieu amplificateur (3) à hétérostructure III-V, chaque réseau de Bragg échantillonné (RBE-A, RBE-B) comprenant un premier réseau de Bragg (RB1-A, RB1B) présentant un premier pas et formé dans l'arête (17) ainsi qu'un second réseau de Bragg (RB2-A, RB2-B) présentant un second pas différent du premier pas et formé sur la face (21) du guide d'onde en ruban (15) opposée à l'arête (17).

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